cpu/vexriscv: update submodule (new linux variant)

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index 66faa6ece6551abac424146f9a27960ba10f4cf8..c6dfccaaa3c830b8c9c5037bbd4e1a8d43ca5bf0 160000 (submodule)
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit 66faa6ece6551abac424146f9a27960ba10f4cf8
+Subproject commit c6dfccaaa3c830b8c9c5037bbd4e1a8d43ca5bf0