* config/tc-msp430.h (DWARF2_ADDR_SIZE): Set to 4.
+2016-02-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/19520
+ * NEWS: Mention new command line option -mrelax-relocations and
+ new configure option --enable-x86-relax-relocations for x86
+ target.
+ * config.in: Regenerated.
+ * configure.ac: Add --enable-x86-relax-relocations.
+ (ac_default_x86_relax_relocations): New. Default to 1 except
+ for x86 Solaris targets older than Solaris 12.
+ (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS): Define.
+ * configure: Likewise.
+ * config/tc-i386.c (generate_relax_relocations): New.
+ (OPTION_MRELAX_RELOCATIONS): Likewise.
+ (output_disp): Don't generate relax relocations if
+ generate_relax_relocations is 0.
+ (md_longopts): Add -mrelax-relocations.
+ (md_show_usage): Likewise.
+ (md_parse_option): Handle OPTION_MRELAX_RELOCATIONS.
+ * doc/c-i386.texi: Document -mrelax-relocations=.
+ * testsuite/gas/i386/got-no-relax.d: New file.
+ * testsuite/gas/i386/x86-64-gotpcrel-no-relax.d: Likewise.
+ * testsuite/gas/i386/got.d: Pass -mrelax-relocations=yes to as.
+ * testsuite/gas/i386/localpic.d: Likewise.
+ * testsuite/gas/i386/mixed-mode-reloc32.d: Likewise.
+ * testsuite/gas/i386/reloc32.d: Likewise.
+ * testsuite/gas/i386/x86-64-gotpcrel.d: Likewise.
+ * testsuite/gas/i386/x86-64-localpic.d: Likewise.
+ * testsuite/gas/i386/ilp32/x86-64-gotpcrel.d: Likewise.
+ * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
+ * testsuite/gas/i386/i386.exp: Run got-no-relax and
+ x86-64-gotpcrel-no-relax.
+
2016-02-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention new command line option -mfence-as-lock-add=yes
-*- text -*-
+* Add a configure option --enable-x86-relax-relocations to decide whether
+ x86 assembler should generate relax relocations by default. Default to
+ yes, except for x86 Solaris targets older than Solaris 12.
+
+* New command line option -mrelax-relocations= for x86 target to control
+ whether to generate relax relocations.
+
* New command line option -mfence-as-lock-add=yes for x86 target to encode
lfence, mfence and sfence as "lock addl $0x0, (%[re]sp)".
/* Define if you want compressed debug sections by default. */
#undef DEFAULT_FLAG_COMPRESS_DEBUG
+/* Define to 1 if you want to generate x86 relax relocations by default. */
+#undef DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
+
/* Supported emulations. */
#undef EMULATIONS
"lock addl $0, (%{re}sp)". */
static int avoid_fence = 0;
+/* 1 if the assembler should generate relax relocations. */
+
+static int generate_relax_relocations
+ = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
+
static enum check_kind
{
check_none = 0,
/* Check for "call/jmp *mem", "mov mem, %reg",
"test %reg, mem" and "binop mem, %reg" where binop
is one of adc, add, and, cmp, or, sbb, sub, xor
- instructions. */
- if ((i.rm.mode == 2
- || (i.rm.mode == 0 && i.rm.regmem == 5))
+ instructions. Always generate R_386_GOT32X for
+ "sym*GOT" operand in 32-bit mode. */
+ if ((generate_relax_relocations
+ || (!object_64bit
+ && i.rm.mode == 0
+ && i.rm.regmem == 5))
+ && (i.rm.mode == 2
+ || (i.rm.mode == 0 && i.rm.regmem == 5))
&& ((i.operands == 1
&& i.tm.base_opcode == 0xff
&& (i.rm.reg == 2 || i.rm.reg == 4))
#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
+#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
struct option md_longopts[] =
{
#endif
{"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
{"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
+ {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
{"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
{"mamd64", no_argument, NULL, OPTION_MAMD64},
{"mintel64", no_argument, NULL, OPTION_MINTEL64},
as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
break;
+ case OPTION_MRELAX_RELOCATIONS:
+ if (strcasecmp (arg, "yes") == 0)
+ generate_relax_relocations = 1;
+ else if (strcasecmp (arg, "no") == 0)
+ generate_relax_relocations = 0;
+ else
+ as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
+ break;
+
case OPTION_MAMD64:
cpu_arch_flags.bitfield.cpuamd64 = 1;
cpu_arch_flags.bitfield.cpuintel64 = 0;
encode lfence, mfence and sfence as\n\
lock addl $0x0, (%%{re}sp)\n"));
fprintf (stream, _("\
+ -mrelax-relocations=[no|yes]\n\
+ generate relax relocations\n"));
+ fprintf (stream, _("\
-mamd64 accept only AMD64 ISA\n"));
fprintf (stream, _("\
-mintel64 accept only Intel64 ISA\n"));
enable_targets
enable_checking
enable_compressed_debug_sections
+enable_x86_relax_relocations
enable_werror
enable_build_warnings
enable_nls
--enable-checking enable run-time checks
--enable-compressed-debug-sections={all,gas,none}
compress debug sections by default
+ --enable-x86-relax-relocations
+ generate x86 relax relocations by default
--enable-werror treat compile warnings as errors
--enable-build-warnings enable build-time compiler warnings
--disable-nls do not use Native Language Support
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 10975 "configure"
+#line 10978 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 11081 "configure"
+#line 11084 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
esac
fi
+# PR gas/19520
+# Decide if x86 assembler should generate relax relocations.
+ac_default_x86_relax_relocations=unset
+# Provide a configure time option to override our default.
+# Check whether --enable-x86_relax_relocations was given.
+if test "${enable_x86_relax_relocations+set}" = set; then :
+ enableval=$enable_x86_relax_relocations; case "${enableval}" in
+ no) ac_default_x86_relax_relocations=0 ;;
+esac
+fi
+
using_cgen=no
;;
+ i386-*-solaris2 \
+ | x86_64-*-solaris2 \
+ | i386-*-solaris2.[0-9] \
+ | i386-*-solaris2.1[01] \
+ | x86_64-*-solaris2.1[01])
+ if test ${this_target} = $target \
+ && test ${ac_default_x86_relax_relocations} = unset; then
+ ac_default_x86_relax_relocations=0
+ fi
+ ;;
+
i860-*-*)
{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: GAS support for ${generic_target} is preliminary and a work in progress" >&5
$as_echo "$as_me: WARNING: GAS support for ${generic_target} is preliminary and a work in progress" >&2;}
done
+if test ${ac_default_x86_relax_relocations} = unset; then
+ ac_default_x86_relax_relocations=1
+fi
+
+cat >>confdefs.h <<_ACEOF
+#define DEFAULT_GENERATE_X86_RELAX_RELOCATIONS $ac_default_x86_relax_relocations
+_ACEOF
+
+
if test x$ac_default_compressed_debug_sections = xyes ; then
$as_echo "#define DEFAULT_FLAG_COMPRESS_DEBUG 1" >>confdefs.h
*) ac_default_compressed_debug_sections=unset ;;
esac])dnl
+# PR gas/19520
+# Decide if x86 assembler should generate relax relocations.
+ac_default_x86_relax_relocations=unset
+# Provide a configure time option to override our default.
+AC_ARG_ENABLE(x86_relax_relocations,
+ AS_HELP_STRING([--enable-x86-relax-relocations],
+ [generate x86 relax relocations by default]),
+[case "${enableval}" in
+ no) ac_default_x86_relax_relocations=0 ;;
+esac])dnl
+
using_cgen=no
AM_BINUTILS_WARNINGS
AC_DEFINE(STRICTCOFF, 1, [Using strict COFF?])
;;
+ i386-*-solaris2 \
+ | x86_64-*-solaris2 \
+ | i386-*-solaris2.[[0-9]] \
+ | i386-*-solaris2.1[[01]] \
+ | x86_64-*-solaris2.1[[01]])
+ if test ${this_target} = $target \
+ && test ${ac_default_x86_relax_relocations} = unset; then
+ ac_default_x86_relax_relocations=0
+ fi
+ ;;
+
i860-*-*)
AC_MSG_WARN(GAS support for ${generic_target} is preliminary and a work in progress)
;;
done
+if test ${ac_default_x86_relax_relocations} = unset; then
+ ac_default_x86_relax_relocations=1
+fi
+AC_DEFINE_UNQUOTED(DEFAULT_GENERATE_X86_RELAX_RELOCATIONS,
+ $ac_default_x86_relax_relocations,
+ [Define to 1 if you want to generate x86 relax relocations by default.])
+
if test x$ac_default_compressed_debug_sections = xyes ; then
AC_DEFINE(DEFAULT_FLAG_COMPRESS_DEBUG, 1, [Define if you want compressed debug sections by default.])
fi
@option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
sfence as usual, which is the default.
+@cindex @samp{-mrelax-relocations=} option, i386
+@cindex @samp{-mrelax-relocations=} option, x86-64
+@item -mrelax-relocations=@var{no}
+@itemx -mrelax-relocations=@var{yes}
+These options control whether the assembler should generate relax
+relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
+R_X86_64_REX_GOTPCRELX, in 64-bit mode.
+@option{-mrelax-relocations=@var{yes}} will generate relax relocations.
+@option{-mrelax-relocations=@var{no}} will not generate relax
+relocations. The default can be controlled by a configure option
+@option{--enable-x86-relax-relocations}.
+
@cindex @samp{-mevexrcig=} option, i386
@cindex @samp{-mevexrcig=} option, x86-64
@item -mevexrcig=@var{rne}
--- /dev/null
+#source: got.s
+#as: -mrelax-relocations=no
+#objdump: -dwr
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax 1: R_386_GOT32 foo
+[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 7: R_386_GOT32X foo
+[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax d: R_386_GOT32 foo
+[ ]*[a-f0-9]+: 05 00 00 00 00 add \$0x0,%eax 12: R_386_GOT32 foo
+[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 18: R_386_GOT32X foo
+[ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 1e: R_386_GOT32 foo
+[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 24: R_386_GOT32X foo
+[ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 2a: R_386_GOT32 foo
+[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 30: R_386_GOT32X foo
+[ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 36: R_386_GOT32 foo
+[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax 3b: R_386_GOT32 foo
+[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 41: R_386_GOT32X foo
+[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax 47: R_386_GOT32 foo
+[ ]*[a-f0-9]+: 05 00 00 00 00 add \$0x0,%eax 4c: R_386_GOT32 foo
+[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 52: R_386_GOT32X foo
+[ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 58: R_386_GOT32 foo
+[ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 5e: R_386_GOT32 foo
+[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 64: R_386_GOT32X foo
+[ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 6a: R_386_GOT32 foo
+[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 70: R_386_GOT32X foo
+#pass
+#as: -mrelax-relocations=yes
#objdump: -dwr
.*: +file format .*
run_dump_test "relax-4"
run_dump_test "got"
+ run_dump_test "got-no-relax"
if {![istarget "*-*-nacl*"]} then {
run_dump_test "iamcu-1"
run_list_test "x86-64-branch-3" "-al -mintel64"
run_dump_test "x86-64-gotpcrel"
+ run_dump_test "x86-64-gotpcrel-no-relax"
}
set ASFLAGS "$old_ASFLAGS"
#source: ../x86-64-gotpcrel.s
+#as: --x32 -mrelax-relocations=yes
#objdump: -dwr
#name: x86-64 (ILP32) gotpcrel
#source: ../x86-64-localpic.s
+#as: --x32 -mrelax-relocations=yes
#readelf: -rsW
#name: x86-64 (ILP32) local PIC
+#as: -mrelax-relocations=yes
#readelf: -rs
#name: i386 local PIC
+#as: -mrelax-relocations=yes
#objdump: -r
#source: mixed-mode-reloc.s
#name: x86 mixed mode relocs (32-bit object)
+#as: -mrelax-relocations=yes
#objdump: -Drw
#name: i386 relocs
--- /dev/null
+#source: x86-64-gotpcrel.s
+#as: -mrelax-relocations=no
+#objdump: -dwr
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 48 c7 c0 00 00 00 00 mov \$0x0,%rax 3: R_X86_64_GOTPCREL foo
+[ ]*[a-f0-9]+: 48 8b 04 25 00 00 00 00 mov 0x0,%rax b: R_X86_64_GOTPCREL foo
+[ ]*[a-f0-9]+: 48 8b 05 00 00 00 00 mov 0x0\(%rip\),%rax # 16 <_start\+0x16> 12: R_X86_64_GOTPCREL foo-0x4
+[ ]*[a-f0-9]+: 48 8b 81 00 00 00 00 mov 0x0\(%rcx\),%rax 19: R_X86_64_GOTPCREL foo
+[ ]*[a-f0-9]+: ff 15 00 00 00 00 callq \*0x0\(%rip\) # 23 <_start\+0x23> 1f: R_X86_64_GOTPCREL foo-0x4
+[ ]*[a-f0-9]+: ff 90 00 00 00 00 callq \*0x0\(%rax\) 25: R_X86_64_GOTPCREL foo
+[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmpq \*0x0\(%rip\) # 2f <_start\+0x2f> 2b: R_X86_64_GOTPCREL foo-0x4
+[ ]*[a-f0-9]+: ff a1 00 00 00 00 jmpq \*0x0\(%rcx\) 31: R_X86_64_GOTPCREL foo
+[ ]*[a-f0-9]+: 48 c7 c0 00 00 00 00 mov \$0x0,%rax 38: R_X86_64_GOTPCREL foo
+[ ]*[a-f0-9]+: 48 8b 04 25 00 00 00 00 mov 0x0,%rax 40: R_X86_64_GOTPCREL foo
+[ ]*[a-f0-9]+: 48 8b 05 00 00 00 00 mov 0x0\(%rip\),%rax # 4b <_start\+0x4b> 47: R_X86_64_GOTPCREL foo-0x4
+[ ]*[a-f0-9]+: 48 8b 81 00 00 00 00 mov 0x0\(%rcx\),%rax 4e: R_X86_64_GOTPCREL foo
+[ ]*[a-f0-9]+: ff 15 00 00 00 00 callq \*0x0\(%rip\) # 58 <_start\+0x58> 54: R_X86_64_GOTPCREL foo-0x4
+[ ]*[a-f0-9]+: ff 90 00 00 00 00 callq \*0x0\(%rax\) 5a: R_X86_64_GOTPCREL foo
+[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmpq \*0x0\(%rip\) # 64 <_start\+0x64> 60: R_X86_64_GOTPCREL foo-0x4
+[ ]*[a-f0-9]+: ff a1 00 00 00 00 jmpq \*0x0\(%rcx\) 66: R_X86_64_GOTPCREL foo
+#pass
+#as: -mrelax-relocations=yes
#objdump: -dwr
.*: +file format .*
+#as: -mrelax-relocations=yes
#readelf: -rsW
#name: x86-64 local PIC
+2016-02-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/19520
+ * testsuite/ld-i386/branch1.d: Pass -mrelax-relocations=yes to as.
+ * testsuite/ld-i386/call1.d: Likewise.
+ * testsuite/ld-i386/call2.d: Likewise.
+ * testsuite/ld-i386/call3a.d: Likewise.
+ * testsuite/ld-i386/call3b.d: Likewise.
+ * testsuite/ld-i386/call3c.d: Likewise.
+ * testsuite/ld-i386/call3d.d: Likewise.
+ * testsuite/ld-i386/call3e.d: Likewise.
+ * testsuite/ld-i386/call3f.d: Likewise.
+ * testsuite/ld-i386/call3g.d: Likewise.
+ * testsuite/ld-i386/call3h.d: Likewise.
+ * testsuite/ld-i386/jmp1.d: Likewise.
+ * testsuite/ld-i386/jmp2.d: Likewise.
+ * testsuite/ld-i386/lea1c.d: Likewise.
+ * testsuite/ld-i386/load1.d: Likewise.
+ * testsuite/ld-i386/load2.d: Likewise.
+ * testsuite/ld-i386/load3.d: Likewise.
+ * testsuite/ld-i386/load4a.d: Likewise.
+ * testsuite/ld-i386/load5a.d: Likewise.
+ * testsuite/ld-i386/mov2b.d: Likewise.
+ * testsuite/ld-i386/mov3.d: Likewise.
+ * testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise.
+ * testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise.
+ * testsuite/ld-ifunc/ifunc-5r-local-x86-64.d: Likewise.
+ * testsuite/ld-x86-64/call1a.d: Likewise.
+ * testsuite/ld-x86-64/call1b.d: Likewise.
+ * testsuite/ld-x86-64/call1c.d: Likewise.
+ * testsuite/ld-x86-64/call1d.d: Likewise.
+ * testsuite/ld-x86-64/call1e.d: Likewise.
+ * testsuite/ld-x86-64/call1f.d: Likewise.
+ * testsuite/ld-x86-64/call1h.d: Likewise.
+ * testsuite/ld-x86-64/call1i.d: Likewise.
+ * testsuite/ld-x86-64/load1a.d: Likewise.
+ * testsuite/ld-x86-64/load1b.d: Likewise.
+ * testsuite/ld-i386/got1a.S: Load GOT into %ecx and use it.
+ * testsuite/ld-i386/got1.dd: Updated.
+ * testsuite/ld-i386/got1d.S (1): Removed.
+ * testsuite/ld-i386/i386.exp: Add -Wa,-mrelax-relocations=yes.
+ * testsuite/ld-x86-64/x86-64.exp: Likewise.
+
2016-02-02 H.J. Lu <hongjiu.lu@intel.com>
PR ld/18591
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -melf_i386
#objdump: -dw
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -shared -melf_i386
#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -shared -melf_i386
#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
#source: call3.s
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -melf_i386
#objdump: -dw
#source: call3.s
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -melf_i386 -z call-nop=prefix-addr
#objdump: -dw
#source: call3.s
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -melf_i386 -z call-nop=prefix-nop
#objdump: -dw
#source: call3.s
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -melf_i386 -z call-nop=suffix-nop
#objdump: -dw
#source: call3.s
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -melf_i386 -z call-nop=prefix-0x67
#objdump: -dw
#source: call3.s
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -melf_i386 -z call-nop=prefix-0x90
#objdump: -dw
#source: call3.s
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -melf_i386 -z call-nop=suffix-0x90
#objdump: -dw
#source: call3.s
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -melf_i386 -z call-nop=suffix-144
#objdump: -dw
[ ]*[a-f0-9]+: ff d0 call \*%eax
[ ]*[a-f0-9]+: [ a-f0-9]+ mov *0x[a-f0-9]+,%eax
[ ]*[a-f0-9]+: ff d0 call \*%eax
+[ ]*[a-f0-9]+: [ a-f0-9]+ call [a-f0-9]+ <__x86.get_pc_thunk.cx>
+[ ]*[a-f0-9]+: [ a-f0-9]+ add \$0x[a-f0-9]+,%ecx
[ ]*[a-f0-9]+: [ a-f0-9]+ lea *0x[a-f0-9]+,%ecx
[ ]*[a-f0-9]+: ff d1 call \*%ecx
[ ]*[a-f0-9]+: 83 ec 0c sub \$0xc,%esp
call *%eax
movl plt@GOT, %eax
call *%eax
- movl foo@GOT(%ebx), %ecx
+ call __x86.get_pc_thunk.cx
+ addl $_GLOBAL_OFFSET_TABLE_, %ecx
+ movl foo@GOT(%ecx), %ecx
call *%ecx
subl $12, %esp
pushl $0
pushl $0 # Push a dummy return address onto stack.
jmp *myexit@GOT
.size main, .-main
+ .section .text.__x86.get_pc_thunk.cx,"axG",@progbits,__x86.get_pc_thunk.cx,comdat
+ .globl __x86.get_pc_thunk.cx
+ .hidden __x86.get_pc_thunk.cx
+ .type __x86.get_pc_thunk.cx, @function
+__x86.get_pc_thunk.cx:
+ movl (%esp), %ecx
+ ret
pushl %esi
pushl %ebx
call __x86.get_pc_thunk.bx
-1:
addl $_GLOBAL_OFFSET_TABLE_, %ebx
subl $20, %esp
leal __FUNCTION__.1866@GOTOFF(%ebx), %esi
[list \
"Build libplt-main1.a" \
"" \
- "-fPIC" \
+ "-fPIC -Wa,-mrelax-relocations=yes" \
{ plt-main1.c } \
{{readelf {-Wr} plt-main1.rd}} \
"libplt-main1.a" \
[list \
"Build libplt-main2.a" \
"" \
- "-fPIC" \
+ "-fPIC -Wa,-mrelax-relocations=yes" \
{ plt-main2.c } \
{{readelf {-Wr} plt-main2.rd}} \
"libplt-main2.a" \
[list \
"Build libplt-main3.a" \
"" \
- "-fPIC $PLT_CFLAGS" \
+ "-fPIC -Wa,-mrelax-relocations=yes $PLT_CFLAGS" \
{ plt-main3.c } \
{{readelf {-Wr} plt-main3.rd}} \
"libplt-main3.a" \
[list \
"Build libplt-main4.a" \
"" \
- "-fPIC $PLT_CFLAGS" \
+ "-fPIC -Wa,-mrelax-relocations=yes $PLT_CFLAGS" \
{ plt-main4.c } \
{{readelf {-Wr} plt-main4.rd}} \
"libplt-main4.a" \
[list \
"Build gotpc1" \
"tmpdir/got1d.so" \
- "" \
+ "-Wa,-mrelax-relocations=yes" \
{ got1a.S got1b.c got1c.c } \
{{objdump {-dw} got1.dd}} \
"got1" \
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -shared -melf_i386
#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -shared -melf_i386
#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
#source: lea1.s
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -melf_i386
#objdump: -dw
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -melf_i386
#objdump: -dw --sym
#notarget: i?86-*-nacl* x86_64-*-nacl*
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -melf_i386 -shared
#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -melf_i386 -shared
#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
#source: load4.s
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -Bsymbolic -shared -melf_i386
#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
#source: load5.s
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -Bsymbolic -shared -melf_i386
#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
#source: mov2.s
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -pie -melf_i386
#objdump: -dw
-#as: --32
+#as: --32 -mrelax-relocations=yes
#ld: -melf_i386
#objdump: -dw
-#as: --64
+#as: --64 -mrelax-relocations=yes
#ld: -melf_x86_64
#objdump: -dw
#target: x86_64-*-*
-#as: --64
+#as: --64 -mrelax-relocations=yes
#ld: -melf_x86_64
#objdump: -dw
#target: x86_64-*-*
#source: ifunc-5-local-x86-64.s
-#as: --64
+#as: --64 -mrelax-relocations=yes
#ld: -r -melf_x86_64
#readelf: -r --wide
#target: x86_64-*-*
#source: call1.s
-#as: --64
+#as: --64 -mrelax-relocations=yes
#ld: -melf_x86_64
#objdump: -dw
#source: call1.s
-#as: --64
+#as: --64 -mrelax-relocations=yes
#ld: -melf_x86_64 -z call-nop=prefix-addr
#objdump: -dw
#source: call1.s
-#as: --64
+#as: --64 -mrelax-relocations=yes
#ld: -melf_x86_64 -z call-nop=prefix-nop
#objdump: -dw
#source: call1.s
-#as: --64
+#as: --64 -mrelax-relocations=yes
#ld: -melf_x86_64 -z call-nop=suffix-nop
#objdump: -dw
#source: call1.s
-#as: --64
+#as: --64 -mrelax-relocations=yes
#ld: -melf_x86_64 -z call-nop=prefix-0x67
#objdump: -dw
#source: call1.s
-#as: --64
+#as: --64 -mrelax-relocations=yes
#ld: -melf_x86_64 -z call-nop=prefix-0x90
#objdump: -dw
#source: call1.s
-#as: --64
+#as: --64 -mrelax-relocations=yes
#ld: -melf_x86_64 -z call-nop=suffix-0x90
#objdump: -dw
#source: call1.s
-#as: --64
+#as: --64 -mrelax-relocations=yes
#ld: -melf_x86_64 -z call-nop=suffix-144
#objdump: -dw
#source: call1.s
-#as: --x32
+#as: --x32 -mrelax-relocations=yes
#ld: -melf32_x86_64 -z call-nop=suffix-0x90
#objdump: -dw
#source: load1.s
-#as: --64
+#as: --64 -mrelax-relocations=yes
#ld: -melf_x86_64
#objdump: -dw --sym
#notarget: x86_64-*-nacl*
#source: load1.s
-#as: --x32
+#as: --x32 -mrelax-relocations=yes
#ld: -melf32_x86_64
#objdump: -dw --sym
#notarget: x86_64-*-nacl*
[list \
"Build libplt-main1.a" \
"" \
- "-fPIC" \
+ "-fPIC -Wa,-mrelax-relocations=yes" \
{ plt-main1.c } \
{{readelf {-Wr} plt-main1.rd}} \
"libplt-main1.a" \
[list \
"Build libplt-main2.a" \
"" \
- "-fPIC" \
+ "-fPIC -Wa,-mrelax-relocations=yes" \
{ plt-main2.c } \
{{readelf {-Wr} plt-main2.rd}} \
"libplt-main2.a" \
[list \
"Build libplt-main3.a" \
"" \
- "-fPIC $PLT_CFLAGS" \
+ "-fPIC -Wa,-mrelax-relocations=yes $PLT_CFLAGS" \
{ plt-main3.c } \
{{readelf {-Wr} plt-main3.rd}} \
"libplt-main3.a" \
[list \
"Build libplt-main4.a" \
"" \
- "-fPIC $PLT_CFLAGS" \
+ "-fPIC -Wa,-mrelax-relocations=yes $PLT_CFLAGS" \
{ plt-main4.c } \
{{readelf {-Wr} plt-main4.rd}} \
"libplt-main4.a" \
[list \
"Build gotpcrel1" \
"tmpdir/gotpcrel1d.so" \
- "" \
+ "-Wa,-mrelax-relocations=yes" \
{ gotpcrel1a.S gotpcrel1b.c gotpcrel1c.c } \
{{objdump {-dw} gotpcrel1.dd}} \
"gotpcrel1" \
projects / binutils-gdb.git / commitdiff