vendor.tinyfpga_b: implement.

diff --git a/nmigen/vendor/fpga/lattice_ice40.py b/nmigen/vendor/fpga/lattice_ice40.py
index 315599973e9f02c490e890e1498562d936d96351..1ca84dc6ba0ad58d62dd52c5ea13a8def880df70 100644 (file)
--- a/nmigen/vendor/fpga/lattice_ice40.py
+++ b/nmigen/vendor/fpga/lattice_ice40.py
@@ -6,7 +6,7 @@ import tempfile
 from ...build import *
 
 
-__all__ = ["LatticeICE40Platform", "IceStormProgrammerMixin", "IceBurnProgrammerMixin"]
+__all__ = ["LatticeICE40Platform", "IceStormProgrammerMixin", "IceBurnProgrammerMixin", "TinyProgrammerMixin"]
 
 
 class LatticeICE40Platform(TemplatedPlatform):
@@ -132,3 +132,13 @@ class IceBurnProgrammerMixin:
         with tempfile.NamedTemporaryFile(prefix="nmigen_iceburn_") as bitstream_file:
             bitstream_file.write(bitstream)
             subprocess.run([iceburn, "-evw", bitstream_file.name], check=True)
+
+
+class TinyProgrammerMixin:
+    def toolchain_program(self, products, name):
+        tinyprog  = os.environ.get("TINYPROG", "tinyprog")
+        options   = ["-p"]
+        bitstream = products.get("{}.bin".format(name))
+        with tempfile.NamedTemporaryFile(prefix="nmigen_tinyprog_") as bitstream_file:
+            bitstream_file.write(bitstream)
+            subprocess.run([tinyprog, *options, bitstream_file.name], check=True)

diff --git a/nmigen/vendor/tinyfpga_b.py b/nmigen/vendor/tinyfpga_b.py
new file mode 100644 (file)
index 0000000..ecb0c58
--- /dev/null
+++ b/nmigen/vendor/tinyfpga_b.py
@@ -0,0 +1,33 @@
+from ..build import *
+from .fpga.lattice_ice40 import LatticeICE40Platform, TinyProgrammerMixin
+
+
+__all__ = ["TinyFPGABPlatform"]
+
+
+class TinyFPGABPlatform(TinyProgrammerMixin, LatticeICE40Platform):
+    device    = "lp8k"
+    package   = "cm81"
+    clocks    = [
+        ("clk16", 16e6),
+    ]
+    resources = [
+        Resource("clk16", 0, Pins("B2", dir="i"), extras=["IO_STANDARD=LVCMOS33"]),
+
+        Resource("user_led", 0, Pins("B3", dir="o"), extras=["IO_STANDARD=LVCMOS33"]),
+
+        Resource("usb", 0,
+            Subsignal("d_p", Pins("B4", dir="io")),
+            Subsignal("d_n", Pins("A4", dir="io")),
+            Subsignal("pull_up", Pins("A3", dir="o")),
+            extras=["IO_STANDARD=SB_LVCMOS33"]
+        ),
+
+        Resource("spiflash", 0,
+            Subsignal("cs_n", Pins("F7", dir="o")),
+            Subsignal("clk",  Pins("G7", dir="o")),
+            Subsignal("mosi", Pins("G6", dir="io")),
+            Subsignal("miso", Pins("H7", dir="io")),
+            extras=["IO_STANDARD=SB_LVCMOS33"]
+        ),
+    ]