preproc: test coverage for #2712

diff --git a/tests/verilog/ifdef_nest.ys b/tests/verilog/ifdef_nest.ys
new file mode 100644 (file)
index 0000000..2202109
--- /dev/null
+++ b/tests/verilog/ifdef_nest.ys
@@ -0,0 +1,7 @@
+read_verilog <<EOF
+`ifndef a
+`ifdef b
+`endif
+`else
+`endif
+EOF

diff --git a/tests/verilog/ifdef_unterminated.ys b/tests/verilog/ifdef_unterminated.ys
new file mode 100644 (file)
index 0000000..ce511fa
--- /dev/null
+++ b/tests/verilog/ifdef_unterminated.ys
@@ -0,0 +1,4 @@
+logger -expect error "Unterminated preprocessor conditional!" 1
+read_verilog <<EOF
+`ifndef a
+EOF

diff --git a/tests/verilog/unmatched_endif_2.ys b/tests/verilog/unmatched_endif_2.ys
new file mode 100644 (file)
index 0000000..2ee0841
--- /dev/null
+++ b/tests/verilog/unmatched_endif_2.ys
@@ -0,0 +1,7 @@
+logger -expect error "Found `endif outside of macro conditional branch!" 1
+read_verilog <<EOF
+`ifndef a
+`else
+`endif
+`endif
+EOF