Work around DDR dout sim glitches in ice40 SB_IO sim model

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index f23218c00aa3f2412ede36ff4ecd35cf20f2db03..7778b551939bf676229d3b402aeccda7f6e3397d 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -47,11 +47,17 @@ module SB_IO (
                din_1 = din_q_1;
        end
 
+       // work around simulation glitches on dout in DDR mode
+       reg outclk_delayed_1;
+       reg outclk_delayed_2;
+       always @* outclk_delayed_1 <= OUTPUT_CLK;
+       always @* outclk_delayed_2 <= outclk_delayed_1;
+
        always @* begin
                if (PIN_TYPE[3])
                        dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
                else
-                       dout = (OUTPUT_CLK ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
+                       dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
        end
 
        assign D_IN_0 = din_0, D_IN_1 = din_1;