For movsf/movdf splits, let movsi define_split handle subword moves

From-SVN: r19340

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bb392977ca32b5d09b9a5c1249c10f8a703aa7a6..8466debe6617e0dcd0bd0849c46d596c204c0907 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+Mon Apr 20 14:48:29 1998  Michael Meissner  <meissner@cygnus.com>
+
+       * rs6000.md (mov{sf,df} define_splits): When splitting a move of
+       a constant to an integer register, don't split the insns that do
+       the simple AND and OR operations, rather just split each word, and
+       let the normal movsi define split handle it further.
+
 Mon Apr 20 18:19:40 1998  J"orn Rennecke <amylaar@cygnus.co.uk>
 
        * sh.c (find_barrier): Fix bug in ADDR_DIFF_VEC handling.

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 71a14e58ee9ecdd3e86b35b8adff366e30010798..b1714b72c36d858947b30d9d1d2e93a857d93667 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1,5 +1,5 @@
 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
-;; Copyright (C) 1990, 91-96, 1997 Free Software Foundation, Inc.
+;; Copyright (C) 1990, 91-96, 1997, 1998 Free Software Foundation, Inc.
 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
 
 ;; This file is part of GNU CC.
@@ -5567,7 +5567,7 @@
 (define_split
   [(set (match_operand:SF 0 "gpc_reg_operand" "")
        (match_operand:SF 1 "const_double_operand" ""))]
-  "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], SFmode) <= 1
+  "TARGET_32BIT && reload_completed
    && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
        || (GET_CODE (operands[0]) == SUBREG
           && GET_CODE (SUBREG_REG (operands[0])) == REG
@@ -5585,29 +5585,6 @@
   operands[3] = GEN_INT(l);
 }")
 
-(define_split
-  [(set (match_operand:SF 0 "gpc_reg_operand" "")
-       (match_operand:SF 1 "const_double_operand" ""))]
-  "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], SFmode) == 2
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-       || (GET_CODE (operands[0]) == SUBREG
-          && GET_CODE (SUBREG_REG (operands[0])) == REG
-          && REGNO (SUBREG_REG (operands[0])) <= 31))"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 4)))]
-  "
-{
-  long l;
-  REAL_VALUE_TYPE rv;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-  REAL_VALUE_TO_TARGET_SINGLE (rv, l);
-
-  operands[2] = operand_subword (operands[0], 0, 0, SFmode);
-  operands[3] = GEN_INT(l & 0xffff0000);
-  operands[4] = GEN_INT(l & 0x0000ffff);
-}")
-
 (define_insn "*movsf_hardfloat"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,!r,!r")
        (match_operand:SF 1 "input_operand" "f,m,f,G,Fn"))]
@@ -5679,7 +5656,7 @@
 (define_split
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
        (match_operand:DF 1 "const_int_operand" ""))]
-  "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) <= 1
+  "TARGET_32BIT && reload_completed
    && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
        || (GET_CODE (operands[0]) == SUBREG
           && GET_CODE (SUBREG_REG (operands[0])) == REG
@@ -5694,32 +5671,10 @@
   operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
 }")
 
-(define_split
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-       (match_operand:DF 1 "const_int_operand" ""))]
-  "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) >= 2
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-       || (GET_CODE (operands[0]) == SUBREG
-          && GET_CODE (SUBREG_REG (operands[0])) == REG
-          && REGNO (SUBREG_REG (operands[0])) <= 31))"
-  [(set (match_dup 3) (match_dup 5))
-   (set (match_dup 2) (match_dup 4))
-   (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 6)))]
-  "
-{
-  HOST_WIDE_INT value = INTVAL (operands[1]);
-  int endian = (WORDS_BIG_ENDIAN == 0);
-  operands[2] = operand_subword (operands[0], endian, 0, DFmode);
-  operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
-  operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
-  operands[5] = GEN_INT (value & 0xffff0000);
-  operands[6] = GEN_INT (value & 0x0000ffff);
-}")
-
 (define_split
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
        (match_operand:DF 1 "const_double_operand" ""))]
-  "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) <= 2
+  "TARGET_32BIT && reload_completed
    && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
        || (GET_CODE (operands[0]) == SUBREG
           && GET_CODE (SUBREG_REG (operands[0])) == REG
@@ -5741,84 +5696,6 @@
   operands[5] = GEN_INT (l[1 - endian]);
 }")
 
-(define_split
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-       (match_operand:DF 1 "const_double_operand" ""))]
-  "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) == 3
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-       || (GET_CODE (operands[0]) == SUBREG
-          && GET_CODE (SUBREG_REG (operands[0])) == REG
-          && REGNO (SUBREG_REG (operands[0])) <= 31))"
-  [(set (match_dup 2) (match_dup 4))
-   (set (match_dup 3) (match_dup 5))
-   (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))]
-  "
-{
-  HOST_WIDE_INT high;
-  HOST_WIDE_INT low;
-  int endian = (WORDS_BIG_ENDIAN == 0);
-  long l[2];
-  REAL_VALUE_TYPE rv;
-  rtx high_reg = operand_subword (operands[0], endian, 0, DFmode);
-  rtx low_reg  = operand_subword (operands[0], 1 - endian, 0, DFmode);
-
-  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-  REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
-  high = l[endian];
-  low  = l[1 - endian];
-
-  if (((unsigned HOST_WIDE_INT) (low + 0x8000) < 0x10000)
-      || (low & 0xffff) == 0)
-    {
-      operands[2] = high_reg;
-      operands[3] = low_reg;
-      operands[4] = GEN_INT (high & 0xffff0000);
-      operands[5] = GEN_INT (low);
-      operands[6] = GEN_INT (high & 0x0000ffff);
-    }
-  else
-    {
-      operands[2] = low_reg;
-      operands[3] = high_reg;
-      operands[4] = GEN_INT (low & 0xffff0000);
-      operands[5] = GEN_INT (high);
-      operands[6] = GEN_INT (low & 0x0000ffff);
-    }
-}")
-
-(define_split
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-       (match_operand:DF 1 "const_double_operand" ""))]
-  "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) >= 4
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-       || (GET_CODE (operands[0]) == SUBREG
-          && GET_CODE (SUBREG_REG (operands[0])) == REG
-          && REGNO (SUBREG_REG (operands[0])) <= 31))"
-  [(set (match_dup 2) (match_dup 4))
-   (set (match_dup 3) (match_dup 5))
-   (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))
-   (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 7)))]
-  "
-{
-  HOST_WIDE_INT high;
-  HOST_WIDE_INT low;
-  long l[2];
-  REAL_VALUE_TYPE rv;
-  int endian = (WORDS_BIG_ENDIAN == 0);
-
-  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-  REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
-  high = l[endian];
-  low  = l[1 - endian];
-
-  operands[2] = operand_subword (operands[0], endian, 0, DFmode);
-  operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
-  operands[4] = GEN_INT (high & 0xffff0000);
-  operands[5] = GEN_INT (low  & 0xffff0000);
-  operands[6] = GEN_INT (high & 0x0000ffff);
-  operands[7] = GEN_INT (low  & 0x0000ffff);
-}")
-
 (define_split
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
        (match_operand:DF 1 "easy_fp_constant" ""))]
@@ -6078,7 +5955,7 @@
 (define_split
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
        (match_operand:DI 1 "const_int_operand" ""))]
-  "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) <= 1"
+  "TARGET_32BIT && reload_completed"
   [(set (match_dup 2) (match_dup 4))
    (set (match_dup 3) (match_dup 1))]
   "
@@ -6088,27 +5965,10 @@
   operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
 }")
 
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-       (match_operand:DI 1 "const_int_operand" ""))]
-  "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) >= 2"
-  [(set (match_dup 3) (match_dup 5))
-   (set (match_dup 2) (match_dup 4))
-   (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 6)))]
-  "
-{
-  HOST_WIDE_INT value = INTVAL (operands[1]);
-  operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
-  operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
-  operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
-  operands[5] = GEN_INT (value & 0xffff0000);
-  operands[6] = GEN_INT (value & 0x0000ffff);
-}")
-
 (define_split
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
        (match_operand:DI 1 "const_double_operand" ""))]
-  "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) <= 2"
+  "TARGET_32BIT && reload_completed"
   [(set (match_dup 2) (match_dup 4))
    (set (match_dup 3) (match_dup 5))]
   "
@@ -6119,60 +5979,6 @@
   operands[5] = GEN_INT (CONST_DOUBLE_LOW  (operands[1]));
 }")
 
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-       (match_operand:DI 1 "const_double_operand" ""))]
-  "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) == 3"
-  [(set (match_dup 2) (match_dup 4))
-   (set (match_dup 3) (match_dup 5))
-   (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))]
-  "
-{
-  HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
-  HOST_WIDE_INT low  = CONST_DOUBLE_LOW  (operands[1]);
-  rtx high_reg = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
-  rtx low_reg  = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
-
-  if (((unsigned HOST_WIDE_INT) (low + 0x8000) < 0x10000)
-      || (low & 0xffff) == 0)
-    {
-      operands[2] = high_reg;
-      operands[3] = low_reg;
-      operands[4] = GEN_INT (high & 0xffff0000);
-      operands[5] = GEN_INT (low);
-      operands[6] = GEN_INT (high & 0x0000ffff);
-    }
-  else
-    {
-      operands[2] = low_reg;
-      operands[3] = high_reg;
-      operands[4] = GEN_INT (low & 0xffff0000);
-      operands[5] = GEN_INT (high);
-      operands[6] = GEN_INT (low & 0x0000ffff);
-    }
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-       (match_operand:DI 1 "const_double_operand" ""))]
-  "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) >= 4"
-  [(set (match_dup 2) (match_dup 4))
-   (set (match_dup 3) (match_dup 5))
-   (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))
-   (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 7)))]
-  "
-{
-  HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
-  HOST_WIDE_INT low  = CONST_DOUBLE_LOW  (operands[1]);
-
-  operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
-  operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
-  operands[4] = GEN_INT (high & 0xffff0000);
-  operands[5] = GEN_INT (low  & 0xffff0000);
-  operands[6] = GEN_INT (high & 0x0000ffff);
-  operands[7] = GEN_INT (low  & 0x0000ffff);
-}")
-
 (define_insn "*movdi_64"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
        (match_operand:DI 1 "input_operand" "r,m,r,I,J,nF,R,f,m,f,*h,r,0"))]