radeon/vcn: add direct register bool
authorBoyuan Zhang <boyuan.zhang@amd.com>
Tue, 5 Mar 2019 22:48:52 +0000 (17:48 -0500)
committerMarek Olšák <marek.olsak@amd.com>
Wed, 3 Jul 2019 19:51:12 +0000 (15:51 -0400)
VCN 2.0 uses direct register space where VCN 1.0 uses some indirect registers

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/gallium/drivers/radeon/radeon_vcn_dec.c
src/gallium/drivers/radeon/radeon_vcn_dec.h

index 99293411b0dc89b694ca148c9875a274c4df7e02..5bc73c1897ec44a6690186cefda4b68f4a56d36d 100644 (file)
@@ -1602,11 +1602,13 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
                dec->reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1;
                dec->reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD;
                dec->reg.cntl = RDECODE_VCN2_ENGINE_CNTL;
+               dec->jpg.direct_reg = true;
        } else {
                dec->reg.data0 = RDECODE_VCN1_GPCOM_VCPU_DATA0;
                dec->reg.data1 = RDECODE_VCN1_GPCOM_VCPU_DATA1;
                dec->reg.cmd = RDECODE_VCN1_GPCOM_VCPU_CMD;
                dec->reg.cntl = RDECODE_VCN1_ENGINE_CNTL;
+               dec->jpg.direct_reg = false;
        }
 
        map_msg_fb_it_probs_buf(dec);
index 3ba42f3b77c87fd0b4974ba0b29c21170e494d75..f079b94dff5ee581466399c18de6c6568459bedd 100644 (file)
@@ -753,6 +753,7 @@ struct jpeg_params {
        unsigned                        dt_uv_pitch;
        unsigned                        dt_luma_top_offset;
        unsigned                        dt_chroma_top_offset;
+       bool                            direct_reg;
 };
 
 struct radeon_decoder {