VCN 2.0 uses direct register space where VCN 1.0 uses some indirect registers
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
dec->reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1;
dec->reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD;
dec->reg.cntl = RDECODE_VCN2_ENGINE_CNTL;
+ dec->jpg.direct_reg = true;
} else {
dec->reg.data0 = RDECODE_VCN1_GPCOM_VCPU_DATA0;
dec->reg.data1 = RDECODE_VCN1_GPCOM_VCPU_DATA1;
dec->reg.cmd = RDECODE_VCN1_GPCOM_VCPU_CMD;
dec->reg.cntl = RDECODE_VCN1_ENGINE_CNTL;
+ dec->jpg.direct_reg = false;
}
map_msg_fb_it_probs_buf(dec);
unsigned dt_uv_pitch;
unsigned dt_luma_top_offset;
unsigned dt_chroma_top_offset;
+ bool direct_reg;
};
struct radeon_decoder {