[ARC] Update (u)maddsidi patterns.
authorClaudiu Zissulescu <claziss@synopsys.com>
Mon, 18 Dec 2017 15:26:47 +0000 (16:26 +0100)
committerClaudiu Zissulescu <claziss@gcc.gnu.org>
Mon, 18 Dec 2017 15:26:47 +0000 (16:26 +0100)
The accumulator registers are freely used by the compiler. However,
there are a number of instructions which are having an intrinsic use
of these registers. Update patterns to inform the compiler which ones.

gcc/
2017-09-19  Claudiu Zissulescu  <claziss@synopsys.com>

* config/arc/arc.md (maddsidi4, maddsidi4_split): Update pattern.
(umaddsidi4,umaddsidi4): Likewise.

gcc/testsuite
2017-09-19  Claudiu Zissulescu  <claziss@synopsys.com>

* gcc.target/arc/tumaddsidi4.c: New test.

From-SVN: r255779

gcc/ChangeLog
gcc/config/arc/arc.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/arc/tumaddsidi4.c [new file with mode: 0755]

index 84046fffb175ddad19da6ef5716159ff274a69a3..5cd14bbaaa9c6f6fe99578698ca391a6400cc662 100644 (file)
@@ -1,3 +1,8 @@
+2017-12-18  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * config/arc/arc.md (maddsidi4, maddsidi4_split): Update pattern.
+       (umaddsidi4, umaddsidi_split): Likewise.
+
 2017-12-18  Claudiu Zissulescu  <claziss@synopsys.com>
 
        * config/arc/arc.c (arc_legitimate_constant_p): Always check all
index 880327c2490c7863646fa9d794efff2637fe0d71..575852e421031c9d62a2cbb0695c11dbeb9b584e 100644 (file)
   [(set_attr "length" "0")])
 
 ;; MAC and DMPY instructions
-(define_insn_and_split "maddsidi4"
+(define_expand "maddsidi4"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:SI 2 "extend_operand"   "")
+   (match_operand:DI 3 "register_operand" "")]
+  "TARGET_PLUS_DMPY"
+  "{
+   emit_insn (gen_maddsidi4_split (operands[0], operands[1], operands[2], operands[3]));
+   DONE;
+  }")
+
+(define_insn_and_split "maddsidi4_split"
   [(set (match_operand:DI 0 "register_operand" "=r")
        (plus:DI
         (mult:DI
          (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
          (sign_extend:DI (match_operand:SI 2 "extend_operand" "ri")))
-        (match_operand:DI 3 "register_operand" "r")))]
+        (match_operand:DI 3 "register_operand" "r")))
+   (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_DMPY"
   "#"
   "TARGET_PLUS_DMPY && reload_completed"
    (set_attr "predicable" "no")
    (set_attr "cond" "nocond")])
 
-(define_insn_and_split "umaddsidi4"
+(define_expand "umaddsidi4"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:SI 2 "extend_operand"   "")
+   (match_operand:DI 3 "register_operand" "")]
+  "TARGET_PLUS_DMPY"
+  "{
+   emit_insn (gen_umaddsidi4_split (operands[0], operands[1], operands[2], operands[3]));
+   DONE;
+  }")
+
+(define_insn_and_split "umaddsidi4_split"
   [(set (match_operand:DI 0 "register_operand" "=r")
        (plus:DI
         (mult:DI
          (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
          (zero_extend:DI (match_operand:SI 2 "extend_operand" "ri")))
-        (match_operand:DI 3 "register_operand" "r")))]
+        (match_operand:DI 3 "register_operand" "r")))
+   (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_DMPY"
   "#"
   "TARGET_PLUS_DMPY && reload_completed"
index 844fc960f7ded45f03c0bf576e98749eea13a6bf..c00a20f79d6e231acd247e9d2a4c15e3ea4f9b46 100644 (file)
@@ -1,3 +1,7 @@
+2017-12-18  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * gcc.target/arc/tumaddsidi4.c: New test.
+
 2017-12-18  Claudiu Zissulescu  <claziss@synopsys.com>
 
        * gcc.target/arc/tls-1.c: New test.
diff --git a/gcc/testsuite/gcc.target/arc/tumaddsidi4.c b/gcc/testsuite/gcc.target/arc/tumaddsidi4.c
new file mode 100755 (executable)
index 0000000..40d2b33
--- /dev/null
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=archs -O1 -mmpy-option=plus_dmpy" } */
+
+/* Check how we generate umaddsidi4 patterns.  */
+long a;
+long long b;
+unsigned c, d;
+
+void fn1(void)
+{
+  b = d * (long long)c + a;
+}
+
+/* { dg-final { scan-assembler "macu 0,r" } } */