Very small differences in IQ-specific O3 stats.
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/dist/binaries/console
+console=/home/stever/m5/m5_system_2.0b3/binaries/console
eventq_index=0
init_param=0
-kernel=/dist/binaries/vmlinux
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
-pal=/dist/binaries/ts_osfpal
-readfile=/work/gem5.latest/tests/halt.sh
+pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu0.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu1.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 29 2014 09:12:51
-gem5 started Oct 29 2014 09:21:02
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
+gem5 compiled Apr 22 2015 07:55:25
+gem5 started Apr 22 2015 09:01:06
+gem5 executing on phenom
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
+
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-info: Launching CPU 1 @ 119596000
-Exiting @ tick 1905067807000 because m5_exit instruction encountered
+info: Launching CPU 1 @ 133655000
+Exiting @ tick 1904437574000 because m5_exit instruction encountered
sim_ticks 1904437574000 # Number of ticks simulated
final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 150033 # Simulator instruction rate (inst/s)
-host_op_rate 150033 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5049661741 # Simulator tick rate (ticks/s)
-host_mem_usage 379720 # Number of bytes of host memory used
-host_seconds 377.14 # Real time elapsed on the host
+host_inst_rate 143053 # Simulator instruction rate (inst/s)
+host_op_rate 143053 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4814720142 # Simulator tick rate (ticks/s)
+host_mem_usage 313028 # Number of bytes of host memory used
+host_seconds 395.54 # Real time elapsed on the host
sim_insts 56583768 # Number of instructions simulated
sim_ops 56583768 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.iq.iqNonSpecInstsAdded 1887245 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 52243998 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 50112 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 6322079 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsExamined 6621677 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 2924940 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 1298251 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 110234726 # Number of insts issued each cycle
system.cpu0.iq.fu_busy_cnt 970450 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.018575 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 215148578 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 61059123 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_writes 61357419 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 50866456 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 594706 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 278076 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_writes 279378 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 273817 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 52889876 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 320091 # Number of floating point alu accesses
system.cpu1.iq.iqNonSpecInstsAdded 487174 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 9053277 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 20996 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 1498950 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedInstsExamined 1564088 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 731721 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 360528 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 13661307 # Number of insts issued each cycle
system.cpu1.iq.fu_busy_cnt 251682 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.027800 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 31870123 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 11194643 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_writes 11259293 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 8718718 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 170415 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 80450 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_writes 80938 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 78899 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 9210850 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 91292 # Number of floating point alu accesses
\rmemcluster 1, usage 0, start 392, end 16384
\rfreeing pages 1069:16384
\rreserving pages 1069:1070
-\r4096K Bcache detected; load hit latency 30 cycles, load miss latency 140 cycles
+\r4096K Bcache detected; load hit latency 30 cycles, load miss latency 154 cycles
\rSMP: 2 CPUs probed -- cpu_present_mask = 3
\rBuilt 1 zonelists
\rKernel command line: root=/dev/hda1 console=ttyS0
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/dist/binaries/console
+console=/home/stever/m5/m5_system_2.0b3/binaries/console
eventq_index=0
init_param=0
-kernel=/dist/binaries/vmlinux
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
-pal=/dist/binaries/ts_osfpal
-readfile=/work/gem5.latest/tests/halt.sh
+pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 29 2014 09:12:51
-gem5 started Oct 29 2014 09:20:51
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
+gem5 compiled Apr 22 2015 07:55:25
+gem5 started Apr 22 2015 08:27:15
+gem5 executing on phenom
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
+
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1859038679000 because m5_exit instruction encountered
+Exiting @ tick 1861005569500 because m5_exit instruction encountered
sim_ticks 1861005569500 # Number of ticks simulated
final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 153218 # Simulator instruction rate (inst/s)
-host_op_rate 153218 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5386630373 # Simulator tick rate (ticks/s)
-host_mem_usage 376136 # Number of bytes of host memory used
-host_seconds 345.49 # Real time elapsed on the host
+host_inst_rate 145313 # Simulator instruction rate (inst/s)
+host_op_rate 145313 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5108711594 # Simulator tick rate (ticks/s)
+host_mem_usage 309496 # Number of bytes of host memory used
+host_seconds 364.28 # Real time elapsed on the host
sim_insts 52934565 # Number of instructions simulated
sim_ops 52934565 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 2136022 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 57539781 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 62715 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 7497440 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 7824422 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3554737 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1474907 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 117014009 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 1115222 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.019382 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 232558247 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 67941522 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 68266797 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 55883323 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 713260 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 334790 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 336497 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 329169 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 58264568 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 383149 # Number of floating point alu accesses
\rmemcluster 1, usage 0, start 392, end 16384
\rfreeing pages 1069:16384
\rreserving pages 1069:1070
-\r4096K Bcache detected; load hit latency 30 cycles, load miss latency 140 cycles
+\r4096K Bcache detected; load hit latency 30 cycles, load miss latency 154 cycles
\rSMP: 1 CPUs probed -- cpu_present_mask = 1
\rBuilt 1 zonelists
\rKernel command line: root=/dev/hda1 console=ttyS0
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/dist/binaries/console
+console=/home/stever/m5/m5_system_2.0b3/binaries/console
eventq_index=0
init_param=0
-kernel=/dist/binaries/vmlinux
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
-pal=/dist/binaries/ts_osfpal
-readfile=/work/gem5.latest/tests/halt.sh
+pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
workload=
[system.cpu2.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu2.dtb]
type=AlphaTLB
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10136, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11138, Bank: 3
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 29 2014 09:12:51
-gem5 started Oct 29 2014 09:24:03
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
+gem5 compiled Apr 22 2015 07:55:25
+gem5 started Apr 22 2015 08:35:45
+gem5 executing on phenom
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
+
Global frequency set at 1000000000000 ticks per second
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
sim_ticks 1841538755500 # Number of ticks simulated
final_tick 1841538755500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 221552 # Simulator instruction rate (inst/s)
-host_op_rate 221552 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5785089232 # Simulator tick rate (ticks/s)
-host_mem_usage 374344 # Number of bytes of host memory used
-host_seconds 318.33 # Real time elapsed on the host
+host_inst_rate 221247 # Simulator instruction rate (inst/s)
+host_op_rate 221247 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5777125497 # Simulator tick rate (ticks/s)
+host_mem_usage 308008 # Number of bytes of host memory used
+host_seconds 318.76 # Real time elapsed on the host
sim_insts 70525499 # Number of instructions simulated
sim_ops 70525499 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu2.iq.iqNonSpecInstsAdded 681806 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 32666998 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 16031 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 2457717 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedInstsExamined 2569271 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 1151235 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 487594 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 29124256 # Number of insts issued each cycle
system.cpu2.iq.fu_busy_cnt 386915 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.011844 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 94607462 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 36013478 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_writes 36124516 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 32054290 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 253736 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 119374 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_writes 119890 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 117198 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 32915380 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 136083 # Number of floating point alu accesses
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM
mem_mode=timing
mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.vram system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
numThreads=1
-predType=bi-mode
[system.cpu.checker]
type=O3Checker
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.checker.dtb
[system.cpu.checker.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[9]
[system.cpu.checker.dtb]
type=ArmTLB
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[7]
+port=system.cpu.toL2Bus.slave[5]
[system.cpu.checker.isa]
type=ArmISA
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.checker.itb
[system.cpu.checker.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[8]
[system.cpu.checker.itb]
type=ArmTLB
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[6]
+port=system.cpu.toL2Bus.slave[4]
[system.cpu.checker.tracer]
type=ExeTracer
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
eventq_index=0
int_latency=10000
it_lines=128
-msix_addr=0
platform=system.realview
system=system
pio=system.membus.master[2]
pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
[system.realview.mmc_fake]
type=AmbaFake
ppint=25
system=system
vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
[system.realview.vram]
type=SimpleMemory
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: 8445832500: Instruction results do not match! (Values may not actually be integers) Inst: 0xa, checker: 0
+warn: 8779058000: Instruction results do not match! (Values may not actually be integers) Inst: 0xa, checker: 0
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
-warn: 81667038500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
+warn: 82000113500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
warn: Returning zero for read from miscreg pmcr
warn: Returning zero for read from miscreg pmcr
warn: Ignoring write to miscreg pmcntenclr
warn: Ignoring write to miscreg pmovsr
warn: Ignoring write to miscreg pmcr
warn: Ignoring write to miscreg pmcr
-warn: CP14 unimplemented crn[12], opc1[5], crm[8], opc2[0]
-warn: 404836653500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
-warn: instruction 'mcr bpiall' unimplemented
+warn: 405408467500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
warn: instruction 'mcr dcisw' unimplemented
+warn: instruction 'mcr bpiall' unimplemented
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 31 2014 10:01:44
-gem5 started Oct 31 2014 11:29:21
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 10:59:45
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
+
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
- 0: system.cpu.checker.isa: ISA system set to: 0x4985680 0x4985680
- 0: system.cpu.isa: ISA system set to: 0x4985680 0x4985680
+info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+ 0: system.cpu.checker.isa: ISA system set to: 0x2d2a120 0x2d2a120
+ 0: system.cpu.isa: ISA system set to: 0x2d2a120 0x2d2a120
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
+info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: Read CNTFREQ_EL0 frequency
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2826844351500 because m5_exit instruction encountered
+Exiting @ tick 2827616186000 because m5_exit instruction encountered
sim_ticks 2827616186000 # Number of ticks simulated
final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 69501 # Simulator instruction rate (inst/s)
-host_op_rate 84304 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1736810486 # Simulator tick rate (ticks/s)
-host_mem_usage 620504 # Number of bytes of host memory used
-host_seconds 1628.05 # Real time elapsed on the host
+host_inst_rate 73888 # Simulator instruction rate (inst/s)
+host_op_rate 89625 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1846444734 # Simulator tick rate (ticks/s)
+host_mem_usage 556020 # Number of bytes of host memory used
+host_seconds 1531.38 # Real time elapsed on the host
sim_insts 113151083 # Number of instructions simulated
sim_ops 137250963 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6274201 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 125312 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 256876545 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 151939321 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 13215 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Apr 20 2015 13:24:23
-gem5 started Apr 20 2015 13:24:39
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 15:52:40
gem5 executing on phenom
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
- 0: system.cpu0.isa: ISA system set to: 0x4157820 0x4157820
- 0: system.cpu1.isa: ISA system set to: 0x4157820 0x4157820
+ 0: system.cpu0.isa: ISA system set to: 0x4163810 0x4163810
+ 0: system.cpu1.isa: ISA system set to: 0x4163810 0x4163810
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
sim_ticks 2625395606000 # Number of ticks simulated
final_tick 2625395606000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 105565 # Simulator instruction rate (inst/s)
-host_op_rate 128079 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2303070285 # Simulator tick rate (ticks/s)
-host_mem_usage 586092 # Number of bytes of host memory used
-host_seconds 1139.95 # Real time elapsed on the host
+host_inst_rate 91005 # Simulator instruction rate (inst/s)
+host_op_rate 110413 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1985416078 # Simulator tick rate (ticks/s)
+host_mem_usage 586088 # Number of bytes of host memory used
+host_seconds 1322.34 # Real time elapsed on the host
sim_insts 120339436 # Number of instructions simulated
sim_ops 146004136 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.iq.iqNonSpecInstsAdded 1660998 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 127592349 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 453825 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 8506052 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsExamined 10488941 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 21267672 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 117222 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 189611039 # Number of insts issued each cycle
system.cpu0.iq.fu_busy_cnt 23403648 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.183425 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 468620138 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 139596675 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_writes 141579564 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 124128658 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 33072 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 11274 # Number of floating instruction queue writes
system.cpu1.iq.iqNonSpecInstsAdded 627473 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 27258527 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 145234 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 2799528 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedInstsExamined 2977146 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 6943190 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 53970 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 42152917 # Number of insts issued each cycle
system.cpu1.iq.fu_busy_cnt 6164373 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.226145 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 102973934 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 31195241 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_writes 31372858 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 26623969 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 5644 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 2049 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_writes 2050 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 1785 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 33419259 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 3574 # Number of floating point alu accesses
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM
mem_mode=timing
mem_ranges=2147483648:2415919103
-memories=system.realview.nvmem system.physmem system.realview.vram
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
numThreads=1
-predType=bi-mode
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
eventq_index=0
int_latency=10000
it_lines=128
-msix_addr=0
platform=system.realview
system=system
pio=system.membus.master[2]
pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
[system.realview.mmc_fake]
type=AmbaFake
ppint=25
system=system
vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
[system.realview.vram]
type=SimpleMemory
warn: Ignoring write to miscreg pmintenclr
warn: Ignoring write to miscreg pmovsr
warn: Ignoring write to miscreg pmcr
-warn: CP14 unimplemented crn[12], opc1[5], crm[8], opc2[0]
-warn: instruction 'mcr bpiall' unimplemented
warn: instruction 'mcr dcisw' unimplemented
+warn: instruction 'mcr bpiall' unimplemented
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 31 2014 10:01:44
-gem5 started Oct 31 2014 11:28:40
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 11:53:00
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
+
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
- 0: system.cpu.isa: ISA system set to: 0x443e680 0x443e680
+info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+ 0: system.cpu.isa: ISA system set to: 0x317f940 0x317f940
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
+info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: Read CNTFREQ_EL0 frequency
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2826844351500 because m5_exit instruction encountered
+Exiting @ tick 2827616186000 because m5_exit instruction encountered
sim_ticks 2827616186000 # Number of ticks simulated
final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 99248 # Simulator instruction rate (inst/s)
-host_op_rate 120386 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2480177298 # Simulator tick rate (ticks/s)
-host_mem_usage 619560 # Number of bytes of host memory used
-host_seconds 1140.09 # Real time elapsed on the host
+host_inst_rate 94820 # Simulator instruction rate (inst/s)
+host_op_rate 115016 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2369528287 # Simulator tick rate (ticks/s)
+host_mem_usage 555256 # Number of bytes of host memory used
+host_seconds 1193.32 # Real time elapsed on the host
sim_insts 113151083 # Number of instructions simulated
sim_ops 137250963 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6274201 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 125312 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 256876545 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 151939321 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 13215 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses
TCP: cubic registered\r
NET: Registered protocol family 10\r
NET: Registered protocol family 17\r
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 12:00:00 UTC (1230811200)\r
+rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)\r
ALSA device list:\r
No soundcards found.\r
\0input: AT Raw Set 2 keyboard as /devices/smb.14/motherboard.15/iofpga.17/1c060000.kmi/serio0/input/input0\r
\rinit started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)\r
\rstarting pid 673, tty '': '/etc/rc.d/rc.local'\r
warning: can't open /etc/mtab: No such file or directory\r
-Thu Jan 1 12:00:02 UTC 2009\r
+Thu Jan 1 00:00:02 UTC 2009\r
S: devpts\r
-Thu Jan 1 12:00:02 UTC 2009\r
+Thu Jan 1 00:00:02 UTC 2009\r
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Apr 20 2015 13:24:23
-gem5 started Apr 20 2015 13:24:39
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 12:26:21
gem5 executing on phenom
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu0.isa: ISA system set to: 0x2ceff00 0x2ceff00
- 0: system.cpu1.isa: ISA system set to: 0x2ceff00 0x2ceff00
- 0: system.cpu2.isa: ISA system set to: 0x2ceff00 0x2ceff00
+ 0: system.cpu0.isa: ISA system set to: 0x305ef00 0x305ef00
+ 0: system.cpu1.isa: ISA system set to: 0x305ef00 0x305ef00
+ 0: system.cpu2.isa: ISA system set to: 0x305ef00 0x305ef00
sim_ticks 2817777605000 # Number of ticks simulated
final_tick 2817777605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 307401 # Simulator instruction rate (inst/s)
-host_op_rate 373266 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6861547245 # Simulator tick rate (ticks/s)
-host_mem_usage 555284 # Number of bytes of host memory used
-host_seconds 410.66 # Real time elapsed on the host
+host_inst_rate 278686 # Simulator instruction rate (inst/s)
+host_op_rate 338399 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6220604315 # Simulator tick rate (ticks/s)
+host_mem_usage 555292 # Number of bytes of host memory used
+host_seconds 452.98 # Real time elapsed on the host
sim_insts 126237777 # Number of instructions simulated
sim_ops 153286368 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu2.iq.iqNonSpecInstsAdded 673336 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 51866821 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 68048 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 7293157 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedInstsExamined 8110099 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 18430167 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 68913 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 67809362 # Number of insts issued each cycle
system.cpu2.iq.fu_busy_cnt 788590 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.015204 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 172390251 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 62545050 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_writes 63361989 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 50322136 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 9391 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 4963 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_writes 4966 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 4144 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 52650258 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 5051 # Number of floating point alu accesses
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM
mem_mode=timing
mem_ranges=2147483648:2415919103
-memories=system.realview.nvmem system.physmem system.realview.vram
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu0.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
workload=
[system.cpu1.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
eventq_index=0
int_latency=10000
it_lines=128
-msix_addr=0
platform=system.realview
system=system
pio=system.membus.master[2]
pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
[system.realview.mmc_fake]
type=AmbaFake
ppint=25
system=system
vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
[system.realview.vram]
type=SimpleMemory
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
[system.vncserver]
type=VncServer
warn: Sockets disabled, not accepting gdb connections
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4]
-warn: CP14 unimplemented crn[8], opc1[4], crm[12], opc2[0]
+warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[3]
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1]
-warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[5]
-warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[1]
+warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3]
+warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3]
warn: Returning zero for read from miscreg pmcr
warn: Ignoring write to miscreg pmcntenclr
warn: Ignoring write to miscreg pmintenclr
warn: Ignoring write to miscreg pmovsr
warn: Ignoring write to miscreg pmcr
-warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[6]
+warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[2]
warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
-warn: CP14 unimplemented crn[4], opc1[5], crm[12], opc2[1]
-warn: CP14 unimplemented crn[5], opc1[4], crm[8], opc2[1]
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0]
+warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[2]
warn: instruction 'mcr bpiall' unimplemented
warn: User mode does not have SPSR
warn: User mode does not have SPSR
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 31 2014 10:01:44
-gem5 started Oct 31 2014 11:48:14
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 11:13:13
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
+
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu0.isa: ISA system set to: 0x4f45680 0x4f45680
- 0: system.cpu1.isa: ISA system set to: 0x4f45680 0x4f45680
+ 0: system.cpu0.isa: ISA system set to: 0x351fd50 0x351fd50
+ 0: system.cpu1.isa: ISA system set to: 0x351fd50 0x351fd50
sim_ticks 2804323403500 # Number of ticks simulated
final_tick 2804323403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 111168 # Simulator instruction rate (inst/s)
-host_op_rate 134929 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2664755466 # Simulator tick rate (ticks/s)
-host_mem_usage 625128 # Number of bytes of host memory used
-host_seconds 1052.38 # Real time elapsed on the host
+host_inst_rate 105186 # Simulator instruction rate (inst/s)
+host_op_rate 127668 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2521360773 # Simulator tick rate (ticks/s)
+host_mem_usage 559780 # Number of bytes of host memory used
+host_seconds 1112.23 # Real time elapsed on the host
sim_insts 116990114 # Number of instructions simulated
sim_ops 141995948 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.iq.iqNonSpecInstsAdded 1058697 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 75784801 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 96696 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 10015024 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsExamined 11308863 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 24599963 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 115562 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 103806101 # Number of insts issued each cycle
system.cpu0.iq.fu_busy_cnt 1102720 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.014551 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 256560915 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 90272679 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_writes 91566516 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 73457837 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 14204 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 7628 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_writes 7630 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 6340 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 76877738 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 7597 # Number of floating point alu accesses
system.cpu1.iq.iqNonSpecInstsAdded 1158159 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 79910900 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 92494 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 10129412 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedInstsExamined 11441232 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 25615832 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 107265 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 106194794 # Number of insts issued each cycle
system.cpu1.iq.fu_busy_cnt 1139082 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.014254 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 267236211 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 94707265 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_writes 96019084 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 77543645 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 11959 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 6289 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_writes 6290 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 5191 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 81043378 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 6453 # Number of floating point alu accesses
TCP: cubic registered\r
NET: Registered protocol family 10\r
NET: Registered protocol family 17\r
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 12:00:00 UTC (1230811200)\r
+rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)\r
ALSA device list:\r
No soundcards found.\r
\0input: AT Raw Set 2 keyboard as /devices/smb.14/motherboard.15/iofpga.17/1c060000.kmi/serio0/input/input0\r
\rinit started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)\r
\rstarting pid 673, tty '': '/etc/rc.d/rc.local'\r
warning: can't open /etc/mtab: No such file or directory\r
-Thu Jan 1 12:00:02 UTC 2009\r
+Thu Jan 1 00:00:02 UTC 2009\r
S: devpts\r
-Thu Jan 1 12:00:02 UTC 2009\r
+Thu Jan 1 00:00:02 UTC 2009\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM64
mem_mode=timing
mem_ranges=2147483648:2415919103
-memories=system.realview.vram system.physmem system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
numThreads=1
-predType=bi-mode
[system.cpu.checker]
type=O3Checker
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.checker.dtb
[system.cpu.checker.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[9]
[system.cpu.checker.dtb]
type=ArmTLB
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[7]
+port=system.cpu.toL2Bus.slave[5]
[system.cpu.checker.isa]
type=ArmISA
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.checker.itb
[system.cpu.checker.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[8]
[system.cpu.checker.itb]
type=ArmTLB
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[6]
+port=system.cpu.toL2Bus.slave[4]
[system.cpu.checker.tracer]
type=ExeTracer
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
eventq_index=0
int_latency=10000
it_lines=128
-msix_addr=0
platform=system.realview
system=system
pio=system.membus.master[2]
pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
[system.realview.mmc_fake]
type=AmbaFake
ppint=25
system=system
vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
[system.realview.vram]
type=SimpleMemory
warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: 12458605972000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d780, checker: 0
+warn: 12458609273000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: 13842443212000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13881966762000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13882255463000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13882829689000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13883384376000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13883639881500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13885195478000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14119823023500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14121701098000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14127958169500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14128186290500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14128405933500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14128812861500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14129226204500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14167422773000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14205629937000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14448292905000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14448293175500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14456513700500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14456513960000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14464465597000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14464465877500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14464466467500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14464466743000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14464466981000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14472409559000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14472410152500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14472410415000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14472410653000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14472410900000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14477663411000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14483940515000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14483940774000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14493678366500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14504940200000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14504941281500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14504941528000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14514859454000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14514859717500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14530591953000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14530592212000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14535730342000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14535730633500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14535731223500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14535731486000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14535731724000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14542816759000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14542817022500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14553011613000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14553012206500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14553012482000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14553012757000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14553013043000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14617580022000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14617580304000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14677231930000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14677232200000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14798881767000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14798974404500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14798974754500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14799704795000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14799705056000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42
-warn: 14799705260500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14799777436500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
-warn: 14799777691500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14799777962500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
-warn: 14799778533000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14799778788500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
-warn: 14799779012000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14799779301000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14799779810000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14799780873500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14799781372500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14799781674500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14848040219000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
-warn: 14848040537000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14848040839000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14848041113000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14848041396500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14848041675500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
+warn: 13847380989000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13886976040500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13909524462000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13910098545500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13910493556500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13910725565500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13910949758000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13919499191000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13969109987000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14211548964500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14211549180000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14219621260500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14227403410000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14227403653500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14227403893000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14227404099500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14235187327500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14235187571000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14235187810500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14235188017000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14240340342500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14240340582000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14246517945500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14246518185000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14256052185500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14256052714000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14256052957500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14256053197000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14256053403500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14267019457500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14267019664000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14276718921000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14276719431500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14276719666000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14276719896500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14276720103000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14292023524000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14292024562000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14292024768500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14297044932500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14297045442000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14297045676000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14297045906000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14297046112500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14313983409500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14313983919000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14313984153000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14313984383000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14313984589500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14376592133500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14376592349000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14434071886000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14434072706000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14434072954500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14434073170000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14562296155000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14562381650500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14562381898500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14562382116000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14562382402000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
+warn: 14562382961000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14562383216500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14562383439500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14562383728500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14562384237500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14562385304500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14562385789500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14562386108000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14563103347000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14563103608000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42
+warn: 14563103812500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14563174588000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
+warn: 14563174798000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14563175069000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
+warn: 14563175639500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14563175895000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
+warn: 14563176118500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14563176407500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14563176916500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14563177979500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14563178471000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14563178773000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14611314421000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
+warn: 14611314697500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14611314949500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14611315194000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14611315463500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14611315702500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 29 2014 09:18:22
-gem5 started Oct 29 2014 10:38:57
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 14:36:18
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker
+
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
- 0: system.cpu.checker.isa: ISA system set to: 0x48ecb00 0x48ecb00
- 0: system.cpu.isa: ISA system set to: 0x48ecb00 0x48ecb00
+info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu.checker.isa: ISA system set to: 0x35ea180 0x35ea180
+ 0: system.cpu.isa: ISA system set to: 0x35ea180 0x35ea180
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 51557114994500 because m5_exit instruction encountered
+Exiting @ tick 51320468905000 because m5_exit instruction encountered
sim_ticks 51320468905000 # Number of ticks simulated
final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 78766 # Simulator instruction rate (inst/s)
-host_op_rate 92549 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4725007878 # Simulator tick rate (ticks/s)
-host_mem_usage 722788 # Number of bytes of host memory used
-host_seconds 10861.46 # Real time elapsed on the host
+host_inst_rate 88986 # Simulator instruction rate (inst/s)
+host_op_rate 104557 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5338089020 # Simulator tick rate (ticks/s)
+host_mem_usage 657992 # Number of bytes of host memory used
+host_seconds 9614.02 # Real time elapsed on the host
sim_insts 855512158 # Number of instructions simulated
sim_ops 1005211605 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 27624460 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1054196021 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 3299994 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 53804457 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 60716319 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 33847358 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 315461 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1530420621 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 165876174 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.157349 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 3805514237 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1118931433 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 1125839347 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1036122901 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 2474593 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 942754 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 946702 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 909865 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1218517790 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1554348 # Number of floating point alu accesses
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000018] Console: colour dummy device 80x25\r
-[ 0.000020] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000021] pid_max: default: 32768 minimum: 301\r
+[ 0.000019] Console: colour dummy device 80x25\r
+[ 0.000021] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000022] pid_max: default: 32768 minimum: 301\r
[ 0.000031] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000032] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000117] hw perfevents: no hardware support available\r
+[ 0.000033] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000120] hw perfevents: no hardware support available\r
[ 1.060065] CPU1: failed to come online\r
[ 2.080127] CPU2: failed to come online\r
[ 3.100189] CPU3: failed to come online\r
-[ 3.100191] Brought up 1 CPUs\r
-[ 3.100192] SMP: Total of 1 processors activated.\r
-[ 3.100238] devtmpfs: initialized\r
-[ 3.100703] atomic64_test: passed\r
-[ 3.100741] regulator-dummy: no parameters\r
-[ 3.101092] NET: Registered protocol family 16\r
-[ 3.101209] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.101216] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.101375] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.101377] Serial: AMBA PL011 UART driver\r
-[ 3.101527] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.101555] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.102087] console [ttyAMA0] enabled\r
-[ 3.102142] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.102172] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.102202] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.102230] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130466] 3V3: 3300 mV \r
-[ 3.130502] vgaarb: loaded\r
-[ 3.130544] SCSI subsystem initialized\r
-[ 3.130580] libata version 3.00 loaded.\r
-[ 3.130622] usbcore: registered new interface driver usbfs\r
-[ 3.130638] usbcore: registered new interface driver hub\r
-[ 3.130668] usbcore: registered new device driver usb\r
-[ 3.130692] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.130701] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.130718] PTP clock support registered\r
-[ 3.130823] Switched to clocksource arch_sys_counter\r
-[ 3.131812] NET: Registered protocol family 2\r
-[ 3.131877] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.131892] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.131910] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.131925] TCP: reno registered\r
-[ 3.131931] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131944] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131977] NET: Registered protocol family 1\r
-[ 3.132021] RPC: Registered named UNIX socket transport module.\r
-[ 3.132031] RPC: Registered udp transport module.\r
-[ 3.132039] RPC: Registered tcp transport module.\r
-[ 3.132046] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.132058] PCI: CLS 0 bytes, default 64\r
-[ 3.132196] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.132285] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.133917] fuse init (API version 7.23)\r
-[ 3.133997] msgmni has been set to 469\r
-[ 3.136058] io scheduler noop registered\r
-[ 3.136109] io scheduler cfq registered (default)\r
-[ 3.136437] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.136449] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.136460] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.136471] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.136481] pci_bus 0000:00: scanning bus\r
-[ 3.136490] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.136502] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.136515] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.136549] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.136561] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.136571] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.136581] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.136591] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.136601] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.136612] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.136645] pci_bus 0000:00: fixups for bus\r
-[ 3.136653] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.136664] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.136680] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.136688] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.136698] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.136706] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.136716] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.136728] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.136741] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.136753] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.136764] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.136774] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.136785] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.136796] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.137238] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.137470] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.137479] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.137497] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.137745] scsi0 : ata_piix\r
-[ 3.137833] scsi1 : ata_piix\r
-[ 3.137862] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.137874] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.137967] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.137978] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.137992] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.138003] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.290845] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.290854] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.290879] ata1.00: configured for UDMA/33\r
-[ 3.290918] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.291021] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.291044] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.291080] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.291088] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.291107] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.291217] sda: sda1\r
-[ 3.291322] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.411114] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.411126] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.411145] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.411155] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.411174] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.411185] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.411250] usbcore: registered new interface driver usb-storage\r
-[ 3.411299] mousedev: PS/2 mouse device common for all mice\r
-[ 3.411439] usbcore: registered new interface driver usbhid\r
-[ 3.411448] usbhid: USB HID core driver\r
-[ 3.411475] TCP: cubic registered\r
-[ 3.411481] NET: Registered protocol family 17\r
-\0[ 3.411782] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.411814] devtmpfs: mounted\r
+[ 3.100192] Brought up 1 CPUs\r
+[ 3.100193] SMP: Total of 1 processors activated.\r
+[ 3.100239] devtmpfs: initialized\r
+[ 3.100662] atomic64_test: passed\r
+[ 3.100699] regulator-dummy: no parameters\r
+[ 3.101056] NET: Registered protocol family 16\r
+[ 3.101171] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.101179] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.101397] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.101401] Serial: AMBA PL011 UART driver\r
+[ 3.101568] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.101599] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.102135] console [ttyAMA0] enabled\r
+[ 3.102203] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 3.102233] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 3.102264] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.102292] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 3.130476] 3V3: 3300 mV \r
+[ 3.130514] vgaarb: loaded\r
+[ 3.130556] SCSI subsystem initialized\r
+[ 3.130592] libata version 3.00 loaded.\r
+[ 3.130632] usbcore: registered new interface driver usbfs\r
+[ 3.130649] usbcore: registered new interface driver hub\r
+[ 3.130678] usbcore: registered new device driver usb\r
+[ 3.130702] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.130710] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.130727] PTP clock support registered\r
+[ 3.130832] Switched to clocksource arch_sys_counter\r
+[ 3.131787] NET: Registered protocol family 2\r
+[ 3.131853] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.131868] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.131886] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.131900] TCP: reno registered\r
+[ 3.131907] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131920] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131953] NET: Registered protocol family 1\r
+[ 3.131998] RPC: Registered named UNIX socket transport module.\r
+[ 3.132008] RPC: Registered udp transport module.\r
+[ 3.132015] RPC: Registered tcp transport module.\r
+[ 3.132023] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.132035] PCI: CLS 0 bytes, default 64\r
+[ 3.132170] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.132259] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.133755] fuse init (API version 7.23)\r
+[ 3.133830] msgmni has been set to 469\r
+[ 3.135876] io scheduler noop registered\r
+[ 3.135924] io scheduler cfq registered (default)\r
+[ 3.136253] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.136265] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.136276] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.136288] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.136297] pci_bus 0000:00: scanning bus\r
+[ 3.136307] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.136319] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.136332] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.136366] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.136377] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.136387] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.136397] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.136408] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.136418] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.136428] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.136460] pci_bus 0000:00: fixups for bus\r
+[ 3.136468] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.136479] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.136497] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.136505] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.136514] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.136522] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.136533] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.136545] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.136557] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.136570] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.136580] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.136591] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.136602] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.136613] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.137039] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.137263] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.137273] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.137291] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.137539] scsi0 : ata_piix\r
+[ 3.137625] scsi1 : ata_piix\r
+[ 3.137652] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.137663] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.137754] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.137765] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.137780] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.137791] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.290854] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.290863] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 3.290888] ata1.00: configured for UDMA/33\r
+[ 3.290928] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.291027] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.291049] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.291085] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.291094] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.291113] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.291218] sda: sda1\r
+[ 3.291320] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.411119] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.411132] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.411151] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.411161] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.411179] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.411190] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.411252] usbcore: registered new interface driver usb-storage\r
+[ 3.411300] mousedev: PS/2 mouse device common for all mice\r
+[ 3.411434] usbcore: registered new interface driver usbhid\r
+[ 3.411443] usbhid: USB HID core driver\r
+[ 3.411470] TCP: cubic registered\r
+[ 3.411477] NET: Registered protocol family 17\r
+\0[ 3.411780] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.411812] devtmpfs: mounted\r
[ 3.411835] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 3.450268] udevd[607]: starting version 182\r
+[ 3.450156] udevd[607]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 3.603357] random: dd urandom read with 21 bits of entropy available\r
+[ 3.543301] random: dd urandom read with 19 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
Mon Jan 27 08:00:00 UTC 2014\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.741050] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+Configuring network interfaces... [ 3.671060] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+udhcpc (v1.21.1) started\r\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM64
mem_mode=timing
mem_ranges=2147483648:2415919103
-memories=system.realview.nvmem system.physmem system.realview.vram
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.branchPred]
-type=BranchPredictor
+type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
numThreads=1
-predType=bi-mode
[system.cpu0.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu0.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
+forward_snoops=false
hit_latency=1
is_top_level=true
max_miss_count=0
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu0.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu0.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu0.l2cache.tags]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
[system.cpu0.tracer]
type=ExeTracer
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.branchPred]
-type=BranchPredictor
+type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
numThreads=1
-predType=bi-mode
[system.cpu1.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu1.toL2Bus.slave[5]
[system.cpu1.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
+forward_snoops=false
hit_latency=1
is_top_level=true
max_miss_count=0
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu1.toL2Bus.slave[4]
[system.cpu1.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu1.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu1.l2cache.tags]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
[system.cpu1.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
eventq_index=0
int_latency=10000
it_lines=128
-msix_addr=0
platform=system.realview
system=system
pio=system.membus.master[2]
pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
[system.realview.mmc_fake]
type=AmbaFake
ppint=25
system=system
vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
[system.realview.vram]
type=SimpleMemory
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: allocating bonus target for snoop
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: allocating bonus target for snoop
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 29 2014 09:18:22
-gem5 started Oct 29 2014 11:56:54
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 13:01:24
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual
+
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
- 0: system.cpu0.isa: ISA system set to: 0x5878b00 0x5878b00
- 0: system.cpu1.isa: ISA system set to: 0x5878b00 0x5878b00
+info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu0.isa: ISA system set to: 0x305baa0 0x305baa0
+ 0: system.cpu1.isa: ISA system set to: 0x305baa0 0x305baa0
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 47379674621500 because m5_exit instruction encountered
+Exiting @ tick 47305566199500 because m5_exit instruction encountered
sim_ticks 47305566199500 # Number of ticks simulated
final_tick 47305566199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 109110 # Simulator instruction rate (inst/s)
-host_op_rate 128307 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5804669404 # Simulator tick rate (ticks/s)
-host_mem_usage 767140 # Number of bytes of host memory used
-host_seconds 8149.57 # Real time elapsed on the host
+host_inst_rate 108918 # Simulator instruction rate (inst/s)
+host_op_rate 128082 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5794473291 # Simulator tick rate (ticks/s)
+host_mem_usage 707548 # Number of bytes of host memory used
+host_seconds 8163.91 # Real time elapsed on the host
sim_insts 889196991 # Number of instructions simulated
sim_ops 1045647845 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.iq.iqNonSpecInstsAdded 14506928 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 587846614 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 2739409 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 51306825 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsExamined 54557687 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 35502721 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 263475 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 706084889 # Number of insts issued each cycle
system.cpu0.iq.fu_busy_cnt 134946779 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.229561 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 2018256641 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 650811943 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_writes 654059965 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 571438682 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 1207660 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 476069 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_writes 478909 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 443638 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 722040340 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 753051 # Number of floating point alu accesses
system.cpu1.iq.iqNonSpecInstsAdded 14979383 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 539826932 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 2475624 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 46992661 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedInstsExamined 50076597 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 32301398 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 273094 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 643136774 # Number of insts issued each cycle
system.cpu1.iq.fu_busy_cnt 122894739 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.227656 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 1846883379 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 597058317 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_writes 600138356 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 524462260 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 1277620 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 514947 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_writes 518844 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 476158 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 661932910 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 788750 # Number of floating point alu accesses
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000013] Console: colour dummy device 80x25\r
-[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000015] pid_max: default: 32768 minimum: 301\r
-[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000089] hw perfevents: no hardware support available\r
-[ 0.060023] CPU1: Booted secondary processor\r
-[ 1.080047] CPU2: failed to come online\r
-[ 2.100092] CPU3: failed to come online\r
-[ 2.100094] Brought up 2 CPUs\r
-[ 2.100095] SMP: Total of 2 processors activated.\r
-[ 2.100128] devtmpfs: initialized\r
-[ 2.100481] atomic64_test: passed\r
-[ 2.100508] regulator-dummy: no parameters\r
-[ 2.100743] NET: Registered protocol family 16\r
-[ 2.100826] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 2.100832] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 2.100987] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 2.100989] Serial: AMBA PL011 UART driver\r
-[ 2.101098] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 2.101119] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 2.101667] console [ttyAMA0] enabled\r
-[ 2.101715] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 2.101742] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 2.101769] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 2.101795] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 2.140191] 3V3: 3300 mV \r
-[ 2.140222] vgaarb: loaded\r
-[ 2.140252] SCSI subsystem initialized\r
-[ 2.140281] libata version 3.00 loaded.\r
-[ 2.140314] usbcore: registered new interface driver usbfs\r
-[ 2.140329] usbcore: registered new interface driver hub\r
-[ 2.140353] usbcore: registered new device driver usb\r
-[ 2.140373] pps_core: LinuxPPS API ver. 1 registered\r
-[ 2.140381] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 2.140399] PTP clock support registered\r
-[ 2.140483] Switched to clocksource arch_sys_counter\r
-[ 2.141463] NET: Registered protocol family 2\r
-[ 2.141511] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 2.141525] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 2.141539] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 2.141554] TCP: reno registered\r
-[ 2.141560] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.141571] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.141596] NET: Registered protocol family 1\r
-[ 2.141634] RPC: Registered named UNIX socket transport module.\r
-[ 2.141644] RPC: Registered udp transport module.\r
-[ 2.141652] RPC: Registered tcp transport module.\r
-[ 2.141660] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 2.141671] PCI: CLS 0 bytes, default 64\r
-[ 2.141775] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 2.141842] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 2.143024] fuse init (API version 7.23)\r
-[ 2.143086] msgmni has been set to 469\r
-[ 2.143317] io scheduler noop registered\r
-[ 2.143357] io scheduler cfq registered (default)\r
-[ 2.143581] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 2.143593] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 2.143603] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 2.143615] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 2.143624] pci_bus 0000:00: scanning bus\r
-[ 2.143633] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 2.143644] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 2.143657] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.143684] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 2.143695] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 2.143705] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 2.143715] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 2.143725] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 2.143735] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 2.143745] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.143773] pci_bus 0000:00: fixups for bus\r
-[ 2.143780] pci_bus 0000:00: bus scan returning with max=00\r
-[ 2.143791] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 2.143806] pci 0000:00:00.0: fixup irq: got 33\r
-[ 2.143814] pci 0000:00:00.0: assigning IRQ 33\r
-[ 2.143823] pci 0000:00:01.0: fixup irq: got 34\r
-[ 2.143831] pci 0000:00:01.0: assigning IRQ 34\r
-[ 2.143840] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 2.143852] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 2.143864] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 2.143876] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 2.143886] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 2.143897] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 2.143907] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 2.143918] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 2.144227] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 2.144396] ata_piix 0000:00:01.0: version 2.13\r
-[ 2.144405] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 2.144421] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 2.144591] scsi0 : ata_piix\r
-[ 2.144642] scsi1 : ata_piix\r
-[ 2.144665] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 2.144676] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 2.144749] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 2.144761] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 2.144773] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 2.144784] e1000 0000:00:00.0: enabling bus mastering\r
-[ 2.290504] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 2.290514] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 2.290536] ata1.00: configured for UDMA/33\r
-[ 2.290567] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 2.290643] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 2.290644] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 2.290661] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 2.290661] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 2.290669] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 2.290760] sda: sda1\r
-[ 2.290840] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 2.410758] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 2.410769] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 2.410788] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 2.410798] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 2.410814] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 2.410826] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 2.410876] usbcore: registered new interface driver usb-storage\r
-[ 2.410921] mousedev: PS/2 mouse device common for all mice\r
-[ 2.411032] usbcore: registered new interface driver usbhid\r
-[ 2.411041] usbhid: USB HID core driver\r
-[ 2.411064] TCP: cubic registered\r
-[ 2.411070] NET: Registered protocol family 17\r
-\0[ 2.411333] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 2.411367] devtmpfs: mounted\r
-[ 2.411386] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 0.000015] Console: colour dummy device 80x25\r
+[ 0.000017] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000018] pid_max: default: 32768 minimum: 301\r
+[ 0.000025] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000026] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000102] hw perfevents: no hardware support available\r
+[ 0.060025] CPU1: Booted secondary processor\r
+[ 1.080050] CPU2: failed to come online\r
+[ 2.100095] CPU3: failed to come online\r
+[ 2.100098] Brought up 2 CPUs\r
+[ 2.100098] SMP: Total of 2 processors activated.\r
+[ 2.100138] devtmpfs: initialized\r
+[ 2.100444] atomic64_test: passed\r
+[ 2.100472] regulator-dummy: no parameters\r
+[ 2.100696] NET: Registered protocol family 16\r
+[ 2.100779] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 2.100786] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 2.100981] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 2.100984] Serial: AMBA PL011 UART driver\r
+[ 2.101110] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 2.101135] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 2.101687] console [ttyAMA0] enabled\r
+[ 2.101755] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 2.101783] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 2.101810] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 2.101836] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 2.140205] 3V3: 3300 mV \r
+[ 2.140237] vgaarb: loaded\r
+[ 2.140268] SCSI subsystem initialized\r
+[ 2.140296] libata version 3.00 loaded.\r
+[ 2.140328] usbcore: registered new interface driver usbfs\r
+[ 2.140342] usbcore: registered new interface driver hub\r
+[ 2.140362] usbcore: registered new device driver usb\r
+[ 2.140381] pps_core: LinuxPPS API ver. 1 registered\r
+[ 2.140390] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 2.140408] PTP clock support registered\r
+[ 2.140494] Switched to clocksource arch_sys_counter\r
+[ 2.141571] NET: Registered protocol family 2\r
+[ 2.141633] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 2.141647] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 2.141662] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 2.141678] TCP: reno registered\r
+[ 2.141685] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.141696] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.141722] NET: Registered protocol family 1\r
+[ 2.141756] RPC: Registered named UNIX socket transport module.\r
+[ 2.141766] RPC: Registered udp transport module.\r
+[ 2.141774] RPC: Registered tcp transport module.\r
+[ 2.141782] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 2.141794] PCI: CLS 0 bytes, default 64\r
+[ 2.141902] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 2.141968] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 2.143005] fuse init (API version 7.23)\r
+[ 2.143061] msgmni has been set to 469\r
+[ 2.143642] io scheduler noop registered\r
+[ 2.143678] io scheduler cfq registered (default)\r
+[ 2.143908] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 2.143920] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 2.143930] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 2.143942] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 2.143952] pci_bus 0000:00: scanning bus\r
+[ 2.143961] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 2.143973] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 2.143986] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.144013] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 2.144024] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 2.144034] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 2.144044] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 2.144054] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 2.144064] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 2.144074] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.144101] pci_bus 0000:00: fixups for bus\r
+[ 2.144108] pci_bus 0000:00: bus scan returning with max=00\r
+[ 2.144119] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 2.144135] pci 0000:00:00.0: fixup irq: got 33\r
+[ 2.144143] pci 0000:00:00.0: assigning IRQ 33\r
+[ 2.144152] pci 0000:00:01.0: fixup irq: got 34\r
+[ 2.144160] pci 0000:00:01.0: assigning IRQ 34\r
+[ 2.144170] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 2.144182] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 2.144195] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 2.144207] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 2.144217] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 2.144228] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 2.144239] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 2.144249] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 2.144543] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 2.144706] ata_piix 0000:00:01.0: version 2.13\r
+[ 2.144715] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 2.144733] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 2.144903] scsi0 : ata_piix\r
+[ 2.144950] scsi1 : ata_piix\r
+[ 2.144971] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 2.144983] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 2.145053] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 2.145065] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 2.145077] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 2.145088] e1000 0000:00:00.0: enabling bus mastering\r
+[ 2.290511] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 2.290521] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 2.290544] ata1.00: configured for UDMA/33\r
+[ 2.290580] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 2.290654] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 2.290656] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 2.290672] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 2.290673] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 2.290680] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 2.290769] sda: sda1\r
+[ 2.290844] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 2.410782] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 2.410795] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 2.410817] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 2.410828] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 2.410848] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 2.410861] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 2.410941] usbcore: registered new interface driver usb-storage\r
+[ 2.410988] mousedev: PS/2 mouse device common for all mice\r
+[ 2.411093] usbcore: registered new interface driver usbhid\r
+[ 2.411103] usbhid: USB HID core driver\r
+[ 2.411126] TCP: cubic registered\r
+[ 2.411133] NET: Registered protocol family 17\r
+\0[ 2.411405] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 2.411442] devtmpfs: mounted\r
+[ 2.411462] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 2.447368] udevd[609]: starting version 182\r
+[ 2.447379] udevd[609]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 2.532352] random: dd urandom read with 18 bits of entropy available\r
+[ 2.532355] random: dd urandom read with 17 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 2.640707] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 2.640722] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM64
mem_mode=timing
mem_ranges=2147483648:2415919103
-memories=system.realview.nvmem system.physmem system.realview.vram
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
numThreads=1
-predType=bi-mode
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
eventq_index=0
int_latency=10000
it_lines=128
-msix_addr=0
platform=system.realview
system=system
pio=system.membus.master[2]
pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
[system.realview.mmc_fake]
type=AmbaFake
ppint=25
system=system
vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
[system.realview.vram]
type=SimpleMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 29 2014 09:18:22
-gem5 started Oct 29 2014 10:37:59
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 12:58:50
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3
+
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
- 0: system.cpu.isa: ISA system set to: 0x43dfb00 0x43dfb00
+info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu.isa: ISA system set to: 0x41ceb00 0x41ceb00
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 51557114994500 because m5_exit instruction encountered
+Exiting @ tick 51320468905000 because m5_exit instruction encountered
sim_ticks 51320468905000 # Number of ticks simulated
final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 114377 # Simulator instruction rate (inst/s)
-host_op_rate 134391 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6861255780 # Simulator tick rate (ticks/s)
-host_mem_usage 720736 # Number of bytes of host memory used
-host_seconds 7479.75 # Real time elapsed on the host
+host_inst_rate 112338 # Simulator instruction rate (inst/s)
+host_op_rate 131995 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6738935517 # Simulator tick rate (ticks/s)
+host_mem_usage 657468 # Number of bytes of host memory used
+host_seconds 7615.52 # Real time elapsed on the host
sim_insts 855512158 # Number of instructions simulated
sim_ops 1005211605 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 27624460 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1054196021 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 3299994 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 53804457 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 60716319 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 33847358 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 315461 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1530420621 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 165876174 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.157349 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 3805514237 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1118931433 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 1125839347 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1036122901 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 2474593 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 942754 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 946702 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 909865 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1218517790 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1554348 # Number of floating point alu accesses
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000018] Console: colour dummy device 80x25\r
-[ 0.000020] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000021] pid_max: default: 32768 minimum: 301\r
+[ 0.000019] Console: colour dummy device 80x25\r
+[ 0.000021] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000022] pid_max: default: 32768 minimum: 301\r
[ 0.000031] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000032] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000117] hw perfevents: no hardware support available\r
+[ 0.000033] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000120] hw perfevents: no hardware support available\r
[ 1.060065] CPU1: failed to come online\r
[ 2.080127] CPU2: failed to come online\r
[ 3.100189] CPU3: failed to come online\r
-[ 3.100191] Brought up 1 CPUs\r
-[ 3.100192] SMP: Total of 1 processors activated.\r
-[ 3.100238] devtmpfs: initialized\r
-[ 3.100703] atomic64_test: passed\r
-[ 3.100741] regulator-dummy: no parameters\r
-[ 3.101092] NET: Registered protocol family 16\r
-[ 3.101209] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.101216] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.101375] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.101377] Serial: AMBA PL011 UART driver\r
-[ 3.101527] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.101555] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.102087] console [ttyAMA0] enabled\r
-[ 3.102142] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.102172] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.102202] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.102230] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130466] 3V3: 3300 mV \r
-[ 3.130502] vgaarb: loaded\r
-[ 3.130544] SCSI subsystem initialized\r
-[ 3.130580] libata version 3.00 loaded.\r
-[ 3.130622] usbcore: registered new interface driver usbfs\r
-[ 3.130638] usbcore: registered new interface driver hub\r
-[ 3.130668] usbcore: registered new device driver usb\r
-[ 3.130692] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.130701] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.130718] PTP clock support registered\r
-[ 3.130823] Switched to clocksource arch_sys_counter\r
-[ 3.131812] NET: Registered protocol family 2\r
-[ 3.131877] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.131892] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.131910] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.131925] TCP: reno registered\r
-[ 3.131931] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131944] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131977] NET: Registered protocol family 1\r
-[ 3.132021] RPC: Registered named UNIX socket transport module.\r
-[ 3.132031] RPC: Registered udp transport module.\r
-[ 3.132039] RPC: Registered tcp transport module.\r
-[ 3.132046] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.132058] PCI: CLS 0 bytes, default 64\r
-[ 3.132196] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.132285] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.133917] fuse init (API version 7.23)\r
-[ 3.133997] msgmni has been set to 469\r
-[ 3.136058] io scheduler noop registered\r
-[ 3.136109] io scheduler cfq registered (default)\r
-[ 3.136437] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.136449] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.136460] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.136471] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.136481] pci_bus 0000:00: scanning bus\r
-[ 3.136490] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.136502] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.136515] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.136549] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.136561] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.136571] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.136581] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.136591] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.136601] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.136612] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.136645] pci_bus 0000:00: fixups for bus\r
-[ 3.136653] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.136664] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.136680] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.136688] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.136698] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.136706] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.136716] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.136728] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.136741] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.136753] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.136764] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.136774] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.136785] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.136796] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.137238] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.137470] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.137479] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.137497] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.137745] scsi0 : ata_piix\r
-[ 3.137833] scsi1 : ata_piix\r
-[ 3.137862] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.137874] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.137967] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.137978] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.137992] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.138003] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.290845] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.290854] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.290879] ata1.00: configured for UDMA/33\r
-[ 3.290918] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.291021] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.291044] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.291080] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.291088] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.291107] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.291217] sda: sda1\r
-[ 3.291322] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.411114] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.411126] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.411145] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.411155] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.411174] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.411185] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.411250] usbcore: registered new interface driver usb-storage\r
-[ 3.411299] mousedev: PS/2 mouse device common for all mice\r
-[ 3.411439] usbcore: registered new interface driver usbhid\r
-[ 3.411448] usbhid: USB HID core driver\r
-[ 3.411475] TCP: cubic registered\r
-[ 3.411481] NET: Registered protocol family 17\r
-\0[ 3.411782] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.411814] devtmpfs: mounted\r
+[ 3.100192] Brought up 1 CPUs\r
+[ 3.100193] SMP: Total of 1 processors activated.\r
+[ 3.100239] devtmpfs: initialized\r
+[ 3.100662] atomic64_test: passed\r
+[ 3.100699] regulator-dummy: no parameters\r
+[ 3.101056] NET: Registered protocol family 16\r
+[ 3.101171] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.101179] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.101397] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.101401] Serial: AMBA PL011 UART driver\r
+[ 3.101568] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.101599] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.102135] console [ttyAMA0] enabled\r
+[ 3.102203] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 3.102233] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 3.102264] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.102292] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 3.130476] 3V3: 3300 mV \r
+[ 3.130514] vgaarb: loaded\r
+[ 3.130556] SCSI subsystem initialized\r
+[ 3.130592] libata version 3.00 loaded.\r
+[ 3.130632] usbcore: registered new interface driver usbfs\r
+[ 3.130649] usbcore: registered new interface driver hub\r
+[ 3.130678] usbcore: registered new device driver usb\r
+[ 3.130702] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.130710] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.130727] PTP clock support registered\r
+[ 3.130832] Switched to clocksource arch_sys_counter\r
+[ 3.131787] NET: Registered protocol family 2\r
+[ 3.131853] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.131868] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.131886] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.131900] TCP: reno registered\r
+[ 3.131907] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131920] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131953] NET: Registered protocol family 1\r
+[ 3.131998] RPC: Registered named UNIX socket transport module.\r
+[ 3.132008] RPC: Registered udp transport module.\r
+[ 3.132015] RPC: Registered tcp transport module.\r
+[ 3.132023] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.132035] PCI: CLS 0 bytes, default 64\r
+[ 3.132170] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.132259] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.133755] fuse init (API version 7.23)\r
+[ 3.133830] msgmni has been set to 469\r
+[ 3.135876] io scheduler noop registered\r
+[ 3.135924] io scheduler cfq registered (default)\r
+[ 3.136253] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.136265] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.136276] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.136288] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.136297] pci_bus 0000:00: scanning bus\r
+[ 3.136307] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.136319] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.136332] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.136366] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.136377] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.136387] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.136397] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.136408] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.136418] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.136428] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.136460] pci_bus 0000:00: fixups for bus\r
+[ 3.136468] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.136479] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.136497] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.136505] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.136514] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.136522] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.136533] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.136545] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.136557] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.136570] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.136580] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.136591] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.136602] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.136613] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.137039] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.137263] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.137273] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.137291] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.137539] scsi0 : ata_piix\r
+[ 3.137625] scsi1 : ata_piix\r
+[ 3.137652] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.137663] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.137754] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.137765] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.137780] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.137791] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.290854] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.290863] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 3.290888] ata1.00: configured for UDMA/33\r
+[ 3.290928] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.291027] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.291049] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.291085] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.291094] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.291113] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.291218] sda: sda1\r
+[ 3.291320] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.411119] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.411132] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.411151] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.411161] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.411179] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.411190] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.411252] usbcore: registered new interface driver usb-storage\r
+[ 3.411300] mousedev: PS/2 mouse device common for all mice\r
+[ 3.411434] usbcore: registered new interface driver usbhid\r
+[ 3.411443] usbhid: USB HID core driver\r
+[ 3.411470] TCP: cubic registered\r
+[ 3.411477] NET: Registered protocol family 17\r
+\0[ 3.411780] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.411812] devtmpfs: mounted\r
[ 3.411835] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 3.450268] udevd[607]: starting version 182\r
+[ 3.450156] udevd[607]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 3.603357] random: dd urandom read with 21 bits of entropy available\r
+[ 3.543301] random: dd urandom read with 19 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
Mon Jan 27 08:00:00 UTC 2014\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.741050] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+Configuring network interfaces... [ 3.671060] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+udhcpc (v1.21.1) started\r\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM64
mem_mode=atomic
mem_ranges=2147483648:2415919103
-memories=system.realview.vram system.physmem system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
workload=
[system.cpu2.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu2.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu2.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu2.dtb
[system.cpu2.dstage2_mmu.stage2_tlb]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu2.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu2.itb
[system.cpu2.istage2_mmu.stage2_tlb]
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
eventq_index=0
int_latency=10000
it_lines=128
-msix_addr=0
platform=system.realview
system=system
pio=system.membus.master[2]
pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
[system.realview.mmc_fake]
type=AmbaFake
ppint=25
system=system
vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
[system.realview.vram]
type=SimpleMemory
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
[system.vncserver]
type=VncServer
warn: Sockets disabled, not accepting gdb connections
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11898, Bank: 3
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8890, Bank: 1
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10682, Bank: 5
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7910, Bank: 6
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6501, Bank: 1
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9251, Bank: 5
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7678, Bank: 1
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6735, Bank: 1
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7557, Bank: 6
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 1
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 3
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6449, Bank: 1
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11346, Bank: 6
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6718, Bank: 7
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8596, Bank: 2
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9274, Bank: 2
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8427, Bank: 5
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7189, Bank: 3
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10975, Bank: 5
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11256, Bank: 2
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6729, Bank: 3
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 12439, Bank: 2
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11356, Bank: 5
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9054, Bank: 7
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6571, Bank: 6
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7539, Bank: 3
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7983, Bank: 5
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7384, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10124, Bank: 1
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 3
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6758, Bank: 2
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8359, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6936, Bank: 1
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8631, Bank: 7
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7482, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8240, Bank: 5
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6884, Bank: 4
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7065, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7992, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 6
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6861, Bank: 4
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6994, Bank: 7
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7102, Bank: 2
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9034, Bank: 2
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10338, Bank: 2
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 29 2014 09:18:22
-gem5 started Oct 29 2014 11:58:52
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 14:18:06
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full
+
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu0.isa: ISA system set to: 0x563eb00 0x563eb00
- 0: system.cpu1.isa: ISA system set to: 0x563eb00 0x563eb00
- 0: system.cpu2.isa: ISA system set to: 0x563eb00 0x563eb00
+ 0: system.cpu0.isa: ISA system set to: 0x47f6c80 0x47f6c80
+ 0: system.cpu1.isa: ISA system set to: 0x47f6c80 0x47f6c80
+ 0: system.cpu2.isa: ISA system set to: 0x47f6c80 0x47f6c80
sim_ticks 51274696167500 # Number of ticks simulated
final_tick 51274696167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 298693 # Simulator instruction rate (inst/s)
-host_op_rate 350975 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 17280969451 # Simulator tick rate (ticks/s)
-host_mem_usage 723560 # Number of bytes of host memory used
-host_seconds 2967.12 # Real time elapsed on the host
+host_inst_rate 281052 # Simulator instruction rate (inst/s)
+host_op_rate 330247 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 16260391227 # Simulator tick rate (ticks/s)
+host_mem_usage 656704 # Number of bytes of host memory used
+host_seconds 3153.35 # Real time elapsed on the host
sim_insts 886256415 # Number of instructions simulated
sim_ops 1041383802 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu2.iq.iqNonSpecInstsAdded 10088471 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 436351243 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 628919 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 55749778 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedInstsExamined 60028880 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 38531819 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 239828 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 444504807 # Number of insts issued each cycle
system.cpu2.iq.fu_busy_cnt 8613137 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.019739 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 1325660566 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 503495404 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_writes 507771301 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 420349481 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 788783 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 388209 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_writes 391414 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 352523 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 444542452 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 421908 # Number of floating point alu accesses
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000011] Console: colour dummy device 80x25\r
-[ 0.000012] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000013] pid_max: default: 32768 minimum: 301\r
-[ 0.000020] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000021] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000065] hw perfevents: no hardware support available\r
+[ 0.000013] Console: colour dummy device 80x25\r
+[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000015] pid_max: default: 32768 minimum: 301\r
+[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000066] hw perfevents: no hardware support available\r
[ 1.060050] CPU1: failed to come online\r
[ 2.080101] CPU2: failed to come online\r
[ 3.100152] CPU3: failed to come online\r
[ 3.100153] Brought up 1 CPUs\r
[ 3.100154] SMP: Total of 1 processors activated.\r
[ 3.100181] devtmpfs: initialized\r
-[ 3.100733] atomic64_test: passed\r
-[ 3.100762] regulator-dummy: no parameters\r
-[ 3.100994] NET: Registered protocol family 16\r
-[ 3.101088] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.101091] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.101130] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.101132] Serial: AMBA PL011 UART driver\r
-[ 3.101419] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.101439] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.100715] atomic64_test: passed\r
+[ 3.100742] regulator-dummy: no parameters\r
+[ 3.100963] NET: Registered protocol family 16\r
+[ 3.101057] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.101060] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.101099] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.101101] Serial: AMBA PL011 UART driver\r
+[ 3.101342] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.101409] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
[ 3.101679] console [ttyAMA0] enabled\r
[ 3.101713] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
[ 3.101727] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.101742] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.101741] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
[ 3.101754] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
[ 3.130360] 3V3: 3300 mV \r
-[ 3.130380] vgaarb: loaded\r
-[ 3.130424] SCSI subsystem initialized\r
-[ 3.130496] libata version 3.00 loaded.\r
-[ 3.130585] usbcore: registered new interface driver usbfs\r
-[ 3.130613] usbcore: registered new interface driver hub\r
-[ 3.130660] usbcore: registered new device driver usb\r
-[ 3.130680] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.130688] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.130704] PTP clock support registered\r
-[ 3.130779] Switched to clocksource arch_sys_counter\r
-[ 3.131645] NET: Registered protocol family 2\r
-[ 3.131698] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.131703] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.131708] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.131711] TCP: reno registered\r
-[ 3.131712] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131715] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131729] NET: Registered protocol family 1\r
-[ 3.131759] RPC: Registered named UNIX socket transport module.\r
-[ 3.131760] RPC: Registered udp transport module.\r
-[ 3.131761] RPC: Registered tcp transport module.\r
-[ 3.131761] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.131763] PCI: CLS 0 bytes, default 64\r
-[ 3.131861] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.131904] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.133537] fuse init (API version 7.23)\r
-[ 3.133689] msgmni has been set to 469\r
-[ 3.135434] io scheduler noop registered\r
-[ 3.135470] io scheduler cfq registered (default)\r
-[ 3.135849] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.135863] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.135875] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.135888] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.135899] pci_bus 0000:00: scanning bus\r
-[ 3.135912] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.135926] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.135942] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.135970] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.135981] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.135990] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.136000] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.136009] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.136018] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.136028] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.136055] pci_bus 0000:00: fixups for bus\r
-[ 3.136062] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.136072] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.136087] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.136095] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.136103] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.136111] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.136120] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.136131] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.136143] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.136154] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.136164] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.136174] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.136185] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.136194] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.136544] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.136816] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.136825] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.136841] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.137006] scsi0 : ata_piix\r
-[ 3.137060] scsi1 : ata_piix\r
-[ 3.137078] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.137079] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.137140] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.137141] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.137145] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.137147] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.290784] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.290786] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.290792] ata1.00: configured for UDMA/33\r
-[ 3.290809] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.290870] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.290878] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.290892] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.290893] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.290900] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.290953] sda: sda1\r
-[ 3.291015] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.411076] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.411091] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.411122] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.411133] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.411166] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.411178] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.411294] usbcore: registered new interface driver usb-storage\r
-[ 3.411333] mousedev: PS/2 mouse device common for all mice\r
-[ 3.411438] usbcore: registered new interface driver usbhid\r
-[ 3.411447] usbhid: USB HID core driver\r
-[ 3.411468] TCP: cubic registered\r
-[ 3.411474] NET: Registered protocol family 17\r
-\0[ 3.411658] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.411668] devtmpfs: mounted\r
-[ 3.411676] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 3.130381] vgaarb: loaded\r
+[ 3.130421] SCSI subsystem initialized\r
+[ 3.130490] libata version 3.00 loaded.\r
+[ 3.130570] usbcore: registered new interface driver usbfs\r
+[ 3.130596] usbcore: registered new interface driver hub\r
+[ 3.130650] usbcore: registered new device driver usb\r
+[ 3.130669] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.130677] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.130694] PTP clock support registered\r
+[ 3.130766] Switched to clocksource arch_sys_counter\r
+[ 3.131600] NET: Registered protocol family 2\r
+[ 3.131646] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.131660] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.131666] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.131669] TCP: reno registered\r
+[ 3.131670] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131673] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131687] NET: Registered protocol family 1\r
+[ 3.131717] RPC: Registered named UNIX socket transport module.\r
+[ 3.131718] RPC: Registered udp transport module.\r
+[ 3.131719] RPC: Registered tcp transport module.\r
+[ 3.131720] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.131721] PCI: CLS 0 bytes, default 64\r
+[ 3.131820] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.131862] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.133297] fuse init (API version 7.23)\r
+[ 3.133349] msgmni has been set to 469\r
+[ 3.135215] io scheduler noop registered\r
+[ 3.135250] io scheduler cfq registered (default)\r
+[ 3.135478] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.135480] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.135481] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.135483] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.135484] pci_bus 0000:00: scanning bus\r
+[ 3.135486] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.135488] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.135491] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.135508] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.135510] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.135511] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.135513] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.135515] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.135516] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.135518] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.135536] pci_bus 0000:00: fixups for bus\r
+[ 3.135537] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.135539] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.135543] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.135545] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.135547] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.135549] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.135551] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.135553] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.135554] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.135556] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.135558] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.135559] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.135561] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.135563] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.136019] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.136176] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.136185] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.136198] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.136386] scsi0 : ata_piix\r
+[ 3.136441] scsi1 : ata_piix\r
+[ 3.136483] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.136496] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.136684] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.136696] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.136709] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.136719] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.290771] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.290772] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 3.290779] ata1.00: configured for UDMA/33\r
+[ 3.290796] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.290857] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.290865] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.290879] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.290880] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.290887] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.290940] sda: sda1\r
+[ 3.291002] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.411060] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.411075] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.411103] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.411114] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.411144] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.411156] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.411274] usbcore: registered new interface driver usb-storage\r
+[ 3.411311] mousedev: PS/2 mouse device common for all mice\r
+[ 3.411407] usbcore: registered new interface driver usbhid\r
+[ 3.411416] usbhid: USB HID core driver\r
+[ 3.411437] TCP: cubic registered\r
+[ 3.411444] NET: Registered protocol family 17\r
+\0[ 3.411630] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.411640] devtmpfs: mounted\r
+[ 3.411648] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 3.449328] udevd[607]: starting version 182\r
+[ 3.449130] udevd[607]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 3.543161] random: dd urandom read with 19 bits of entropy available\r
+[ 3.543090] random: dd urandom read with 19 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.661005] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 3.660992] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM64
mem_mode=timing
mem_ranges=2147483648:2415919103
-memories=system.realview.vram system.physmem system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu0.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
workload=
[system.cpu1.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
eventq_index=0
int_latency=10000
it_lines=128
-msix_addr=0
platform=system.realview
system=system
pio=system.membus.master[2]
pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
[system.realview.mmc_fake]
type=AmbaFake
ppint=25
system=system
vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
[system.realview.vram]
type=SimpleMemory
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
[system.vncserver]
type=VncServer
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 29 2014 15:46:15
-gem5 started Oct 29 2014 19:59:19
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 15:04:42
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3
+
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu0.isa: ISA system set to: 0x42b8b00 0x42b8b00
- 0: system.cpu1.isa: ISA system set to: 0x42b8b00 0x42b8b00
+ 0: system.cpu0.isa: ISA system set to: 0x40189d0 0x40189d0
+ 0: system.cpu1.isa: ISA system set to: 0x40189d0 0x40189d0
sim_ticks 51318118168000 # Number of ticks simulated
final_tick 51318118168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 134411 # Simulator instruction rate (inst/s)
-host_op_rate 157933 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 7593762336 # Simulator tick rate (ticks/s)
-host_mem_usage 732664 # Number of bytes of host memory used
-host_seconds 6757.93 # Real time elapsed on the host
+host_inst_rate 135924 # Simulator instruction rate (inst/s)
+host_op_rate 159711 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7679227340 # Simulator tick rate (ticks/s)
+host_mem_usage 666876 # Number of bytes of host memory used
+host_seconds 6682.72 # Real time elapsed on the host
sim_insts 908340493 # Number of instructions simulated
sim_ops 1067303522 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.iq.iqNonSpecInstsAdded 15856672 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 599090036 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 857856 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 76035125 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsExamined 81807793 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 52627296 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 360655 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 646873994 # Number of insts issued each cycle
system.cpu0.iq.fu_busy_cnt 11885426 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.019839 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 1856813329 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 690194574 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_writes 695962848 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 576693438 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 984019 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 484790 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_writes 489184 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 438468 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 610449620 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 525838 # Number of floating point alu accesses
system.cpu1.iq.iqNonSpecInstsAdded 15287986 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 601499543 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 865295 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 76155843 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedInstsExamined 81943902 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 52376442 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 362406 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 643871402 # Number of insts issued each cycle
system.cpu1.iq.fu_busy_cnt 11593896 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.019275 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 1858238935 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 693444958 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_writes 699228429 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 579923061 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 1090744 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 536293 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_writes 540881 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 488146 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 612510547 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 582891 # Number of floating point alu accesses
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
[ 0.000011] Console: colour dummy device 80x25\r
[ 0.000013] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000013] pid_max: default: 32768 minimum: 301\r
+[ 0.000014] pid_max: default: 32768 minimum: 301\r
[ 0.000020] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
[ 0.000021] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000090] hw perfevents: no hardware support available\r
+[ 0.000091] hw perfevents: no hardware support available\r
[ 1.060050] CPU1: failed to come online\r
[ 2.080096] CPU2: failed to come online\r
[ 3.100142] CPU3: failed to come online\r
-[ 3.100144] Brought up 1 CPUs\r
+[ 3.100145] Brought up 1 CPUs\r
[ 3.100145] SMP: Total of 1 processors activated.\r
-[ 3.100180] devtmpfs: initialized\r
-[ 3.100498] atomic64_test: passed\r
-[ 3.100526] regulator-dummy: no parameters\r
-[ 3.100758] NET: Registered protocol family 16\r
-[ 3.100838] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.100845] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.101001] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.101002] Serial: AMBA PL011 UART driver\r
-[ 3.101107] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.101127] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.101646] console [ttyAMA0] enabled\r
-[ 3.101688] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.101712] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.101737] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.101761] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130353] 3V3: 3300 mV \r
-[ 3.130382] vgaarb: loaded\r
-[ 3.130412] SCSI subsystem initialized\r
-[ 3.130441] libata version 3.00 loaded.\r
-[ 3.130473] usbcore: registered new interface driver usbfs\r
-[ 3.130487] usbcore: registered new interface driver hub\r
-[ 3.130511] usbcore: registered new device driver usb\r
-[ 3.130530] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.130538] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.130554] PTP clock support registered\r
-[ 3.130630] Switched to clocksource arch_sys_counter\r
-[ 3.131365] NET: Registered protocol family 2\r
-[ 3.131410] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.131424] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.131439] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.131453] TCP: reno registered\r
-[ 3.131459] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131470] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131496] NET: Registered protocol family 1\r
-[ 3.131539] RPC: Registered named UNIX socket transport module.\r
-[ 3.131548] RPC: Registered udp transport module.\r
-[ 3.131555] RPC: Registered tcp transport module.\r
-[ 3.131563] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.131574] PCI: CLS 0 bytes, default 64\r
-[ 3.131673] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.131735] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.132928] fuse init (API version 7.23)\r
-[ 3.132989] msgmni has been set to 469\r
-[ 3.134506] io scheduler noop registered\r
-[ 3.134546] io scheduler cfq registered (default)\r
-[ 3.134769] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.134780] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.134790] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.134801] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.134810] pci_bus 0000:00: scanning bus\r
-[ 3.134819] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.134830] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.134842] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.134869] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.134880] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.134889] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.134899] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.134908] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.134918] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.134928] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.134955] pci_bus 0000:00: fixups for bus\r
-[ 3.134962] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.134972] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.134987] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.134995] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.135003] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.135011] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.135020] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.135031] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.135043] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.135054] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.135065] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.135075] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.135085] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.135095] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.135422] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.135591] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.135600] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.135616] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.135788] scsi0 : ata_piix\r
-[ 3.135855] scsi1 : ata_piix\r
-[ 3.135877] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.135888] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.135958] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.135969] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.135982] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.135992] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.290650] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.100181] devtmpfs: initialized\r
+[ 3.100445] atomic64_test: passed\r
+[ 3.100472] regulator-dummy: no parameters\r
+[ 3.100688] NET: Registered protocol family 16\r
+[ 3.100765] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.100772] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.100985] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.100989] Serial: AMBA PL011 UART driver\r
+[ 3.101109] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.101131] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.101654] console [ttyAMA0] enabled\r
+[ 3.101707] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 3.101732] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 3.101757] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.101781] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 3.130360] 3V3: 3300 mV \r
+[ 3.130388] vgaarb: loaded\r
+[ 3.130419] SCSI subsystem initialized\r
+[ 3.130448] libata version 3.00 loaded.\r
+[ 3.130477] usbcore: registered new interface driver usbfs\r
+[ 3.130491] usbcore: registered new interface driver hub\r
+[ 3.130515] usbcore: registered new device driver usb\r
+[ 3.130533] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.130542] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.130558] PTP clock support registered\r
+[ 3.130631] Switched to clocksource arch_sys_counter\r
+[ 3.131314] NET: Registered protocol family 2\r
+[ 3.131359] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.131373] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.131388] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.131401] TCP: reno registered\r
+[ 3.131407] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131418] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131445] NET: Registered protocol family 1\r
+[ 3.131486] RPC: Registered named UNIX socket transport module.\r
+[ 3.131496] RPC: Registered udp transport module.\r
+[ 3.131503] RPC: Registered tcp transport module.\r
+[ 3.131511] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.131522] PCI: CLS 0 bytes, default 64\r
+[ 3.131616] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.131677] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.132690] fuse init (API version 7.23)\r
+[ 3.132744] msgmni has been set to 469\r
+[ 3.134228] io scheduler noop registered\r
+[ 3.134263] io scheduler cfq registered (default)\r
+[ 3.134485] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.134497] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.134507] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.134518] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.134527] pci_bus 0000:00: scanning bus\r
+[ 3.134536] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.134547] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.134559] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.134585] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.134596] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.134605] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.134615] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.134624] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.134634] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.134644] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.134669] pci_bus 0000:00: fixups for bus\r
+[ 3.134676] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.134687] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.134702] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.134710] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.134718] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.134726] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.134735] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.134747] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.134759] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.134770] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.134780] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.134790] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.134801] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.134811] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.135117] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.135275] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.135284] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.135300] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.135469] scsi0 : ata_piix\r
+[ 3.135531] scsi1 : ata_piix\r
+[ 3.135551] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.135562] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.135629] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.135640] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.135652] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.135662] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.290651] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
[ 3.290659] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.290681] ata1.00: configured for UDMA/33\r
-[ 3.290713] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.290793] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.290812] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.290843] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.290851] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.290867] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.290956] sda: sda1\r
-[ 3.291038] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.410906] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.410918] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.410934] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.410944] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.410960] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.410970] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.411019] usbcore: registered new interface driver usb-storage\r
-[ 3.411058] mousedev: PS/2 mouse device common for all mice\r
-[ 3.411163] usbcore: registered new interface driver usbhid\r
-[ 3.411172] usbhid: USB HID core driver\r
-[ 3.411193] TCP: cubic registered\r
-[ 3.411200] NET: Registered protocol family 17\r
-\0[ 3.411427] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.411454] devtmpfs: mounted\r
-[ 3.411473] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 3.290682] ata1.00: configured for UDMA/33\r
+[ 3.290714] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.290788] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.290807] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.290836] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.290845] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.290861] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.290945] sda: sda1\r
+[ 3.291020] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.410902] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.410913] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.410930] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.410939] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.410954] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.410965] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.411010] usbcore: registered new interface driver usb-storage\r
+[ 3.411047] mousedev: PS/2 mouse device common for all mice\r
+[ 3.411142] usbcore: registered new interface driver usbhid\r
+[ 3.411151] usbhid: USB HID core driver\r
+[ 3.411173] TCP: cubic registered\r
+[ 3.411179] NET: Registered protocol family 17\r
+\0[ 3.411405] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.411432] devtmpfs: mounted\r
+[ 3.411453] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 3.448022] udevd[607]: starting version 182\r
+[ 3.447823] udevd[607]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 3.542571] random: dd urandom read with 19 bits of entropy available\r
+[ 3.542531] random: dd urandom read with 19 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.660858] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 3.660859] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Apr 20 2015 13:24:00
-gem5 started Apr 20 2015 13:25:09
+gem5 compiled Apr 22 2015 08:10:29
+gem5 started Apr 22 2015 10:12:51
gem5 executing on phenom
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
sim_ticks 5154239928000 # Number of ticks simulated
final_tick 5154239928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 179131 # Simulator instruction rate (inst/s)
-host_op_rate 354077 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2263170239 # Simulator tick rate (ticks/s)
-host_mem_usage 759084 # Number of bytes of host memory used
-host_seconds 2277.44 # Real time elapsed on the host
+host_inst_rate 159835 # Simulator instruction rate (inst/s)
+host_op_rate 315937 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2019388964 # Simulator tick rate (ticks/s)
+host_mem_usage 759104 # Number of bytes of host memory used
+host_seconds 2552.38 # Real time elapsed on the host
sim_insts 407959851 # Number of instructions simulated
sim_ops 806389826 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 1196558 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 824230120 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 243416 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 23349289 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 24276361 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 36028466 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 151024 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 449344124 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 2760609 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.003349 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 2100807897 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 854027763 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 854954817 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 819692227 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 491 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 488 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 506 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 826700185 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
kernel_addr_check=true
load_addr_mask=18446744073709551615
load_offset=0
mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
-readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
workload=
[system.cpu2.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu2.dtb]
type=X86TLB
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=false
-width=8
+width=16
default=system.pc.pciconfig.pio
master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.physmem.port
slave=system.apicbridge.master system.system_port system.l2c.mem_side system.cpu0.interrupts.int_master system.iocache.mem_side
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-x86.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
"name": null,
"sim_quantum": 0,
"system": {
- "kernel": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9",
- "l2c": {
- "is_top_level": false,
- "prefetcher": null,
- "clk_domain": "system.cpu_clk_domain",
- "write_buffers": 8,
- "response_latency": 20,
- "cxx_class": "BaseCache",
- "size": 4194304,
- "tags": {
- "name": "tags",
- "eventq_index": 0,
- "hit_latency": 20,
- "clk_domain": "system.cpu_clk_domain",
- "sequential_access": false,
- "assoc": 8,
- "cxx_class": "LRU",
- "path": "system.l2c.tags",
- "block_size": 64,
- "type": "LRU",
- "size": 4194304
- },
- "system": "system",
- "max_miss_count": 0,
- "eventq_index": 0,
- "mem_side": {
- "peer": "system.membus.slave[2]",
- "role": "MASTER"
- },
- "mshrs": 20,
- "forward_snoops": true,
- "hit_latency": 20,
- "demand_mshr_reserve": 1,
- "tgts_per_mshr": 12,
- "addr_ranges": [
- "0:18446744073709551615"
- ],
- "assoc": 8,
- "prefetch_on_access": false,
- "path": "system.l2c",
- "name": "l2c",
- "type": "BaseCache",
- "sequential_access": false,
- "cpu_side": {
- "peer": "system.toL2Bus.master[0]",
- "role": "SLAVE"
- },
- "two_queue": false
- },
+ "kernel": "/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9",
+ "mmap_using_noreserve": false,
"kernel_addr_check": true,
"bridge": {
"ranges": [
"peer": "system.pc.pciconfig.pio",
"role": "MASTER"
},
+ "forward_latency": 1,
"clk_domain": "system.clk_domain",
- "header_cycles": 1,
- "width": 8,
+ "width": 16,
"eventq_index": 0,
"master": {
"peer": [
],
"role": "MASTER"
},
+ "response_latency": 2,
"cxx_class": "NoncoherentXBar",
"path": "system.iobus",
"type": "NoncoherentXBar",
- "use_default_range": false
+ "use_default_range": false,
+ "frontend_latency": 2
},
"apicbridge": {
"ranges": [
"type": "Bridge"
},
"symbolfile": "",
- "readfile": "/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh",
+ "l2c": {
+ "is_top_level": false,
+ "prefetcher": null,
+ "clk_domain": "system.cpu_clk_domain",
+ "write_buffers": 8,
+ "response_latency": 20,
+ "cxx_class": "BaseCache",
+ "size": 4194304,
+ "tags": {
+ "name": "tags",
+ "eventq_index": 0,
+ "hit_latency": 20,
+ "clk_domain": "system.cpu_clk_domain",
+ "sequential_access": false,
+ "assoc": 8,
+ "cxx_class": "LRU",
+ "path": "system.l2c.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "size": 4194304
+ },
+ "system": "system",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "mem_side": {
+ "peer": "system.membus.slave[2]",
+ "role": "MASTER"
+ },
+ "mshrs": 20,
+ "forward_snoops": true,
+ "hit_latency": 20,
+ "demand_mshr_reserve": 1,
+ "tgts_per_mshr": 12,
+ "addr_ranges": [
+ "0:18446744073709551615"
+ ],
+ "assoc": 8,
+ "prefetch_on_access": false,
+ "path": "system.l2c",
+ "name": "l2c",
+ "type": "BaseCache",
+ "sequential_access": false,
+ "cpu_side": {
+ "peer": "system.toL2Bus.master[0]",
+ "role": "SLAVE"
+ },
+ "two_queue": false
+ },
+ "readfile": "/home/stever/hg/m5sim.org/gem5/tests/halt.sh",
"intel_mp_table": {
"oem_table_addr": 0,
"name": "intel_mp_table",
"ret_data16": 65535
},
"snoop_filter": null,
+ "forward_latency": 4,
"clk_domain": "system.clk_domain",
- "header_cycles": 1,
"system": "system",
- "width": 8,
+ "width": 16,
"eventq_index": 0,
"master": {
"peer": [
],
"role": "MASTER"
},
+ "response_latency": 2,
"cxx_class": "CoherentXBar",
"path": "system.membus",
+ "snoop_response_latency": 4,
"type": "CoherentXBar",
- "use_default_range": false
+ "use_default_range": false,
+ "frontend_latency": 3
},
"pc": {
"fake_com_4": {
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.pc.south_bridge.ide.disks0.image.child",
- "image_file": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-x86.img",
+ "image_file": "/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img",
"type": "RawDiskImage"
},
"path": "system.pc.south_bridge.ide.disks0.image",
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.pc.south_bridge.ide.disks1.image.child",
- "image_file": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-bigswap2.img",
+ "image_file": "/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img",
"type": "RawDiskImage"
},
"path": "system.pc.south_bridge.ide.disks1.image",
"path": "system.physmem",
"tXP": 0,
"tXS": 0,
- "addr_mapping": "RoRaBaChCo",
+ "addr_mapping": "RoRaBaCoCh",
"IDD3P0": "0.0",
"IDD3P1": "0.0",
"IDD3N": "0.057",
},
"name": "toL2Bus",
"snoop_filter": null,
+ "forward_latency": 0,
"clk_domain": "system.cpu_clk_domain",
- "header_cycles": 1,
"system": "system",
- "width": 8,
+ "width": 32,
"eventq_index": 0,
"master": {
"peer": [
],
"role": "MASTER"
},
+ "response_latency": 1,
"cxx_class": "CoherentXBar",
"path": "system.toL2Bus",
+ "snoop_response_latency": 1,
"type": "CoherentXBar",
- "use_default_range": false
+ "use_default_range": false,
+ "frontend_latency": 1
},
"work_end_ckpt_count": 0,
"mem_mode": "atomic",
"eventq_index": 0,
"BTBTagSize": 16,
"BTBEntries": 4096,
- "cxx_class": "BPredUnit",
+ "cxx_class": "TournamentBP",
"path": "system.cpu2.branchPred",
"localPredictorSize": 2048,
- "type": "BranchPredictor",
- "predType": "tournament",
+ "type": "TournamentBP",
"RASSize": 16,
"globalPredictorSize": 8192
},
warn: Sockets disabled, not accepting gdb connections
warn: Reading current count from inactive timer.
warn: Don't know what interrupt to clear for console.
+warn: x86 cpuid: unknown family 0xbacc
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11155, Bank: 3
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
-Command: 0, Timestamp: 10068, Bank: 3
+Command: 0, Timestamp: 8139, Bank: 7
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7686, Bank: 3
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11067, Bank: 2
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6494, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6532, Bank: 6
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 2
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
-Command: 0, Timestamp: 11102, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7271, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8628, Bank: 5
+Command: 0, Timestamp: 10283, Bank: 3
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: Tried to clear PCI interrupt 14
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: Unknown mouse command 0xe1.
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: Tried to clear PCI interrupt 14
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7809, Bank: 2
+WARNING: Bank is already active!
+Command: 0, Timestamp: 12253, Bank: 7
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7886, Bank: 4
+warn: Unknown mouse command 0xe1.
warn: instruction 'wbinvd' unimplemented
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is not active!
+Command: 1, Timestamp: 1481, Bank: 4
+WARNING: Bank is not active!
+Command: 1, Timestamp: 2142, Bank: 4
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 6 2015 22:19:56
-gem5 started Jan 6 2015 22:27:08
-gem5 executing on gabeblackz620.mtv.corp.google.com
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /usr/local/google/home/gabeblack/gem5/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
+gem5 compiled Apr 22 2015 08:10:29
+gem5 started Apr 22 2015 10:40:08
+gem5 executing on phenom
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
+
Global frequency set at 1000000000000 ticks per second
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
sim_ticks 5134220888000 # Number of ticks simulated
final_tick 5134220888000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 274165 # Simulator instruction rate (inst/s)
-host_op_rate 545049 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5772363280 # Simulator tick rate (ticks/s)
-host_mem_usage 1013712 # Number of bytes of host memory used
-host_seconds 889.45 # Real time elapsed on the host
+host_inst_rate 243170 # Simulator instruction rate (inst/s)
+host_op_rate 483430 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5119785775 # Simulator tick rate (ticks/s)
+host_mem_usage 964244 # Number of bytes of host memory used
+host_seconds 1002.82 # Real time elapsed on the host
sim_insts 243855553 # Number of instructions simulated
sim_ops 484792888 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu2.iq.iqNonSpecInstsAdded 432383 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 277466645 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 109952 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 9178493 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedInstsExamined 9552955 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 14257252 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 68980 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 154648109 # Number of insts issued each cycle
system.cpu2.iq.fu_busy_cnt 1946922 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.007017 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 711637991 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 289314219 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_writes 289688673 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 275821613 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 281 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 236 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_writes 244 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 279330355 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 137 # Number of floating point alu accesses
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
Initializing CPU#0\r
PID hash table entries: 512 (order: 9, 4096 bytes)\r
-time.c: Detected 2000.002 MHz processor.\r
+time.c: Detected 2000.007 MHz processor.\r
Console: colour dummy device 80x25\r
console handover: boot [earlyser0] -> real [ttyS0]\r
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]\r
ACPI: Unable to load the System Description Tables\r
Using local APIC timer interrupts.\r
-result 7812526\r
+result 7812546\r
Detected 7.812 MHz APIC timer.\r
NET: Registered protocol family 16\r
PCI: Using configuration type 1\r
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
numThreads=1
-predType=bi-mode
[system.cpu.dcache]
type=BaseCache
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
+forward_snoops=false
hit_latency=1
is_top_level=true
max_miss_count=0
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
max_stack_size=67108864
output=cout
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 21:33:12
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 11:34:28
gem5 executing on phenom
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x666d940
+ 0: system.cpu.isa: ISA system set to: 0 0x299b730
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 26894328500 because target called exit()
+Exiting @ tick 58202727500 because target called exit()
sim_ticks 58202727500 # Number of ticks simulated
final_tick 58202727500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 129726 # Simulator instruction rate (inst/s)
-host_op_rate 130372 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 83346935 # Simulator tick rate (ticks/s)
-host_mem_usage 443628 # Number of bytes of host memory used
-host_seconds 698.32 # Real time elapsed on the host
+host_inst_rate 129301 # Simulator instruction rate (inst/s)
+host_op_rate 129945 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 83074382 # Simulator tick rate (ticks/s)
+host_mem_usage 373768 # Number of bytes of host memory used
+host_seconds 700.61 # Real time elapsed on the host
sim_insts 90589798 # Number of instructions simulated
sim_ops 91041029 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 8246 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 101389982 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1073881 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 18465721 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 18662119 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 41703174 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 116352474 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 20109961 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.198343 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 340315821 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 128169527 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 128365920 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 99626078 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 459 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 609 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 614 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 121499704 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
eventq_index=0
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
max_stack_size=67108864
output=cout
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:13:07
-gem5 started Jun 21 2014 16:50:55
+gem5 compiled Apr 22 2015 08:10:29
+gem5 started Apr 22 2015 09:28:24
gem5 executing on phenom
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
nodes : 500
active arcs : 1905
simplex iterations : 1502
-info: Increasing stack size by one page.
flow value : 4990014995
new implicit arcs : 23867
active arcs : 25772
simplex iterations : 2663
+info: Increasing stack size by one page.
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 64361067000 because target called exit()
+Exiting @ tick 62113055500 because target called exit()
sim_ticks 62113055500 # Number of ticks simulated
final_tick 62113055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 113198 # Simulator instruction rate (inst/s)
-host_op_rate 199324 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44503726 # Simulator tick rate (ticks/s)
-host_mem_usage 454072 # Number of bytes of host memory used
-host_seconds 1395.68 # Real time elapsed on the host
+host_inst_rate 109820 # Simulator instruction rate (inst/s)
+host_op_rate 193376 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 43175715 # Simulator tick rate (ticks/s)
+host_mem_usage 386160 # Number of bytes of host memory used
+host_seconds 1438.61 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 2126 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 307989355 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 51384 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 46683880 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 47286965 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 68913858 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1681 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 124161279 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 4211210 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013673 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 744402178 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 372203676 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 372806758 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 305987015 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 405 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 722 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 146 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 312167028 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
numThreads=1
-predType=bi-mode
[system.cpu.dcache]
type=BaseCache
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
+forward_snoops=false
hit_latency=1
is_top_level=true
max_miss_count=0
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/parser
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 21:42:28
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 11:19:35
gem5 executing on phenom
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x6824800
+ 0: system.cpu.isa: ISA system set to: 0 0x3ca3710
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 201639641000 because target called exit()
+Exiting @ tick 233381523500 because target called exit()
sim_ticks 233381523500 # Number of ticks simulated
final_tick 233381523500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 139639 # Simulator instruction rate (inst/s)
-host_op_rate 151279 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 64502789 # Simulator tick rate (ticks/s)
-host_mem_usage 317896 # Number of bytes of host memory used
-host_seconds 3618.16 # Real time elapsed on the host
+host_inst_rate 138194 # Simulator instruction rate (inst/s)
+host_op_rate 149713 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 63835070 # Simulator tick rate (ticks/s)
+host_mem_usage 248488 # Number of bytes of host memory used
+host_seconds 3656.01 # Real time elapsed on the host
sim_insts 505237723 # Number of instructions simulated
sim_ops 547350944 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 2978333 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 610244720 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 5860928 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 122748160 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 123796022 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 319249921 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 701 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 465881386 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 135784339 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.222508 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1828015800 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 793923222 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 794971084 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 594984495 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
eventq_index=0
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:13:07
-gem5 started Jun 21 2014 22:34:22
+gem5 compiled Apr 22 2015 08:10:29
+gem5 started Apr 22 2015 09:35:25
gem5 executing on phenom
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
- Reading the dictionary files: *********info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-******************************info: Increasing stack size by one page.
+ Reading the dictionary files: *******info: Increasing stack size by one page.
+**info: Increasing stack size by one page.
+**************************************info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
-**********
+**
58924 words stored in 3784810 bytes
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 456433328000 because target called exit()
+Exiting @ tick 455715234500 because target called exit()
sim_ticks 455715234500 # Number of ticks simulated
final_tick 455715234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 71545 # Simulator instruction rate (inst/s)
-host_op_rate 132294 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 39430208 # Simulator tick rate (ticks/s)
-host_mem_usage 421584 # Number of bytes of host memory used
-host_seconds 11557.52 # Real time elapsed on the host
+host_inst_rate 95556 # Simulator instruction rate (inst/s)
+host_op_rate 176693 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 52663419 # Simulator tick rate (ticks/s)
+host_mem_usage 364636 # Number of bytes of host memory used
+host_seconds 8653.35 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 24468 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1829137533 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 426447 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 579133879 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 583823860 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1007575077 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 23916 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 911228208 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 26638041 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.014563 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4596535787 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2692210314 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 2696900293 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1799537822 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 31975 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 69900 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 69902 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6901 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1853040947 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 14852 # Number of floating point alu accesses
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
kvmInSE=false
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 19 2014 12:27:06
-gem5 started Jul 19 2014 12:27:28
+gem5 compiled Apr 22 2015 07:55:25
+gem5 started Apr 22 2015 08:19:59
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.066667
-Exiting @ tick 72880000500 because target called exit()
+Exiting @ tick 69793219500 because target called exit()
sim_ticks 69793219500 # Number of ticks simulated
final_tick 69793219500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 248568 # Simulator instruction rate (inst/s)
-host_op_rate 248568 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 46191499 # Simulator tick rate (ticks/s)
-host_mem_usage 302704 # Number of bytes of host memory used
-host_seconds 1510.95 # Real time elapsed on the host
+host_inst_rate 237836 # Simulator instruction rate (inst/s)
+host_op_rate 237836 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44197170 # Simulator tick rate (ticks/s)
+host_mem_usage 232228 # Number of bytes of host memory used
+host_seconds 1579.13 # Real time elapsed on the host
sim_insts 375574808 # Number of instructions simulated
sim_ops 375574808 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 308 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 407272286 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 487219 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 39326693 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 39472187 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 18379010 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 139281263 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 19969288 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.049032 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 626696170 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 266696972 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 266819247 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 237458259 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 347586172 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 187752417 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 187775636 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 163387975 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 246426590 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 180781403 # Number of floating point alu accesses
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
numThreads=1
-predType=bi-mode
[system.cpu.dcache]
type=BaseCache
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
+forward_snoops=false
hit_latency=1
is_top_level=true
max_miss_count=0
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
kvmInSE=false
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 21:42:59
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 11:46:25
gem5 executing on phenom
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x6560400
+ 0: system.cpu.isa: ISA system set to: 0 0x2c9dca0
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
-OO-style eon Time= 0.060000
-Exiting @ tick 64766858000 because target called exit()
+OO-style eon Time= 0.110000
+Exiting @ tick 112553814500 because target called exit()
sim_ticks 112553814500 # Number of ticks simulated
final_tick 112553814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 125235 # Simulator instruction rate (inst/s)
-host_op_rate 150358 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 51625290 # Simulator tick rate (ticks/s)
-host_mem_usage 326264 # Number of bytes of host memory used
-host_seconds 2180.21 # Real time elapsed on the host
+host_inst_rate 123079 # Simulator instruction rate (inst/s)
+host_op_rate 147770 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50736526 # Simulator tick rate (ticks/s)
+host_mem_usage 257068 # Number of bytes of host memory used
+host_seconds 2218.40 # Real time elapsed on the host
sim_insts 273037219 # Number of instructions simulated
sim_ops 327811601 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 28024 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 346404668 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 2300304 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 24831082 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 25451552 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 73599170 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 5904 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 224784448 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 124292517 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.358807 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 756686876 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 251306416 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 251708205 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 223263085 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 287499729 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 126798006 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 127016687 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 117424806 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 303164482 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 167532703 # Number of floating point alu accesses
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=LiveProcess
cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
+drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 19 2014 12:27:06
-gem5 started Jul 19 2014 12:27:27
+gem5 compiled Apr 22 2015 07:55:25
+gem5 started Apr 22 2015 08:48:44
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
-1375000: 2038431008
-1374000: 3487365506
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+Exiting @ tick 279668927000 because target called exit()
sim_ticks 279668927000 # Number of ticks simulated
final_tick 279668927000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 180963 # Simulator instruction rate (inst/s)
-host_op_rate 180963 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 60079385 # Simulator tick rate (ticks/s)
-host_mem_usage 306712 # Number of bytes of host memory used
-host_seconds 4654.99 # Real time elapsed on the host
+host_inst_rate 172383 # Simulator instruction rate (inst/s)
+host_op_rate 172383 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 57230702 # Simulator tick rate (ticks/s)
+host_mem_usage 232716 # Number of bytes of host memory used
+host_seconds 4886.69 # Real time elapsed on the host
sim_insts 842382029 # Number of instructions simulated
sim_ops 842382029 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 89 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1016009395 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 8790765 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 462565445 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 462590577 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 427723515 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 52 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 559092875 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 23622740 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.023251 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 2552720615 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1726495098 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 1726519951 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 940123896 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 70804555 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 41088088 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 41088367 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 34423394 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1003270759 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 36360100 # Number of floating point alu accesses
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
numThreads=1
-predType=bi-mode
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
+forward_snoops=false
hit_latency=1
is_top_level=true
max_miss_count=0
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu.l2cache.tags]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=LiveProcess
cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
+drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: fcntl64(3, 2) passed through to host
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 21:43:02
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 11:51:12
gem5 executing on phenom
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x5c9e4b0
+ 0: system.cpu.isa: ISA system set to: 0 0x36128d0
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
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+Exiting @ tick 409399480000 because target called exit()
sim_ticks 409399480000 # Number of ticks simulated
final_tick 409399480000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 93383 # Simulator instruction rate (inst/s)
-host_op_rate 114967 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 59675446 # Simulator tick rate (ticks/s)
-host_mem_usage 317532 # Number of bytes of host memory used
-host_seconds 6860.43 # Real time elapsed on the host
+host_inst_rate 92444 # Simulator instruction rate (inst/s)
+host_op_rate 113811 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 59075206 # Simulator tick rate (ticks/s)
+host_mem_usage 244496 # Number of bytes of host memory used
+host_seconds 6930.14 # Real time elapsed on the host
sim_insts 640649298 # Number of instructions simulated
sim_ops 788724957 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1017122920 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 18523621 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 379819992 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 379926855 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1032577011 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 818460793 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 337415663 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.331735 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 3146768879 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1504924384 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 1505031237 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 934270592 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 61877038 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 43565805 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 43565815 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 26152443 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1320728240 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 33810343 # Number of floating point alu accesses
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
kvmInSE=false
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 19 2014 12:27:06
-gem5 started Jul 19 2014 12:27:28
+gem5 compiled Apr 22 2015 07:55:25
+gem5 started Apr 22 2015 08:46:29
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 24220559500 because target called exit()
+Exiting @ tick 22578120000 because target called exit()
sim_ticks 22578120000 # Number of ticks simulated
final_tick 22578120000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 224564 # Simulator instruction rate (inst/s)
-host_op_rate 224564 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 63702871 # Simulator tick rate (ticks/s)
-host_mem_usage 305848 # Number of bytes of host memory used
-host_seconds 354.43 # Real time elapsed on the host
+host_inst_rate 210348 # Simulator instruction rate (inst/s)
+host_op_rate 210348 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 59670380 # Simulator tick rate (ticks/s)
+host_mem_usage 234940 # Number of bytes of host memory used
+host_seconds 378.38 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 5639 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 89055311 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 77552 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 11218941 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 11713229 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 4714239 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1056 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 44368516 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 2523465 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.028336 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 224465346 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 102111433 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 102605449 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 87163804 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 614809 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 433572 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 433844 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 300747 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 91271228 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 307548 # Number of floating point alu accesses
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
numThreads=1
-predType=bi-mode
[system.cpu.dcache]
type=BaseCache
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
+forward_snoops=false
hit_latency=1
is_top_level=true
max_miss_count=0
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
kvmInSE=false
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 21:43:42
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 11:16:00
gem5 executing on phenom
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x62769a0
+ 0: system.cpu.isa: ISA system set to: 0 0x3dc8200
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 25431292500 because target called exit()
+Exiting @ tick 33359312000 because target called exit()
sim_ticks 33359312000 # Number of ticks simulated
final_tick 33359312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 125450 # Simulator instruction rate (inst/s)
-host_op_rate 160435 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 59019201 # Simulator tick rate (ticks/s)
-host_mem_usage 322444 # Number of bytes of host memory used
-host_seconds 565.23 # Real time elapsed on the host
+host_inst_rate 119579 # Simulator instruction rate (inst/s)
+host_op_rate 152928 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 56257417 # Simulator tick rate (ticks/s)
+host_mem_usage 252556 # Number of bytes of host memory used
+host_seconds 592.98 # Real time elapsed on the host
sim_insts 70907629 # Number of instructions simulated
sim_ops 90682584 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 34522 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 94891849 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 694587 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 7414208 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 7518802 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 20250811 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 736 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 65867882 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 29960509 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.315733 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 286306469 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 105626883 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 105731477 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 93465742 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
kvmInSE=false
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 19 2014 12:27:06
-gem5 started Jul 19 2014 12:27:27
+gem5 compiled Apr 22 2015 07:55:25
+gem5 started Apr 22 2015 08:36:02
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 679349778000 because target called exit()
+Exiting @ tick 672881519500 because target called exit()
sim_ticks 672881519500 # Number of ticks simulated
final_tick 672881519500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 171066 # Simulator instruction rate (inst/s)
-host_op_rate 171066 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 66304234 # Simulator tick rate (ticks/s)
-host_mem_usage 296744 # Number of bytes of host memory used
-host_seconds 10148.39 # Real time elapsed on the host
+host_inst_rate 165835 # Simulator instruction rate (inst/s)
+host_op_rate 165835 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 64276745 # Simulator tick rate (ticks/s)
+host_mem_usage 226308 # Number of bytes of host memory used
+host_seconds 10468.51 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2624396643 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1584497 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 1140831193 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 1154325126 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 506084435 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1345692377 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 36787651 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.014018 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6630876089 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 4030049566 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 4043543263 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2522176401 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 1981722 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1296863 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 1297099 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 893189 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2660200136 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 984158 # Number of floating point alu accesses
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
numThreads=1
-predType=bi-mode
[system.cpu.dcache]
type=BaseCache
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
+forward_snoops=false
hit_latency=1
is_top_level=true
max_miss_count=0
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
kvmInSE=false
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 21:45:58
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 12:38:48
gem5 executing on phenom
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x5287000
+ 0: system.cpu.isa: ISA system set to: 0 0x39c9fd0
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 523063504500 because target called exit()
+Exiting @ tick 771782683000 because target called exit()
sim_ticks 771782683000 # Number of ticks simulated
final_tick 771782683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 141348 # Simulator instruction rate (inst/s)
-host_op_rate 152281 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 70628369 # Simulator tick rate (ticks/s)
-host_mem_usage 310548 # Number of bytes of host memory used
-host_seconds 10927.38 # Real time elapsed on the host
+host_inst_rate 140791 # Simulator instruction rate (inst/s)
+host_op_rate 151681 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 70349895 # Simulator tick rate (ticks/s)
+host_mem_usage 240068 # Number of bytes of host memory used
+host_seconds 10970.63 # Real time elapsed on the host
sim_insts 1544563023 # Number of instructions simulated
sim_ops 1664032415 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 210 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1857409514 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 13500100 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 279518916 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 283851537 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 646881302 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1543486763 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 405102720 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.218101 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5676908390 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2227415601 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 2231748222 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1805707256 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 208 # Number of floating instruction queue writes
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
kvmInSE=false
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 19 2014 12:27:06
-gem5 started Jul 19 2014 12:27:28
+gem5 compiled Apr 22 2015 07:55:25
+gem5 started Apr 22 2015 08:19:48
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
+
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 23058360500 because target called exit()
+122 123 124 Exiting @ tick 22228749500 because target called exit()
sim_ticks 22228749500 # Number of ticks simulated
final_tick 22228749500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 212613 # Simulator instruction rate (inst/s)
-host_op_rate 212613 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 56143360 # Simulator tick rate (ticks/s)
-host_mem_usage 300388 # Number of bytes of host memory used
-host_seconds 395.93 # Real time elapsed on the host
+host_inst_rate 192800 # Simulator instruction rate (inst/s)
+host_op_rate 192800 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50911418 # Simulator tick rate (ticks/s)
+host_mem_usage 230228 # Number of bytes of host memory used
+host_seconds 436.62 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 2237 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 100145020 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 122649 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 28075682 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 28567051 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 21979359 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1848 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 44211553 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 2379738 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.023763 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 231363005 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 131215529 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 131706335 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 90039702 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 15640975 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 9648680 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 9649243 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 7175345 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 94170320 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 8354431 # Number of floating point alu accesses
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
numThreads=1
-predType=bi-mode
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
+forward_snoops=false
hit_latency=1
is_top_level=true
max_miss_count=0
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu.l2cache.tags]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=LiveProcess
cmd=twolf smred
cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
+drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 21:53:28
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 12:02:59
gem5 executing on phenom
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
+
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x4f074c0
+ 0: system.cpu.isa: ISA system set to: 0 0x2e8fab0
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 74056845500 because target called exit()
+122 123 124 Exiting @ tick 85027009000 because target called exit()
sim_ticks 85027009000 # Number of ticks simulated
final_tick 85027009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 134467 # Simulator instruction rate (inst/s)
-host_op_rate 141751 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 66356016 # Simulator tick rate (ticks/s)
-host_mem_usage 312828 # Number of bytes of host memory used
-host_seconds 1281.38 # Real time elapsed on the host
+host_inst_rate 123827 # Simulator instruction rate (inst/s)
+host_op_rate 130534 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 61105425 # Simulator tick rate (ticks/s)
+host_mem_usage 242728 # Number of bytes of host memory used
+host_seconds 1391.48 # Real time elapsed on the host
sim_insts 172303021 # Number of instructions simulated
sim_ops 181635953 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 45858 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 214907174 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 5191222 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 82643318 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 83234167 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 219950944 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 642 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 169913124 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 53853149 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.250588 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 654819591 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 345508564 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 346099299 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 204603377 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3952252 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2011834 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 2011948 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 1806382 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 266627232 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2133091 # Number of floating point alu accesses
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
eventq_index=0
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
kvmInSE=false
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 28 2014 04:02:39
-gem5 started Aug 28 2014 04:26:16
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
+gem5 compiled Apr 22 2015 08:10:29
+gem5 started Apr 22 2015 10:10:22
+gem5 executing on phenom
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
+
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Increasing stack size by one page.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 31 32 33 34 35 36 37 38 39 40 41 42 info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+ 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 145755370500 because target called exit()
+122 123 124 Exiting @ tick 148668850500 because target called exit()
sim_ticks 148668850500 # Number of ticks simulated
final_tick 148668850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 82634 # Simulator instruction rate (inst/s)
-host_op_rate 138502 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 93018548 # Simulator tick rate (ticks/s)
-host_mem_usage 346916 # Number of bytes of host memory used
-host_seconds 1598.27 # Real time elapsed on the host
+host_inst_rate 74389 # Simulator instruction rate (inst/s)
+host_op_rate 124683 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 83737935 # Simulator tick rate (ticks/s)
+host_mem_usage 279976 # Number of bytes of host memory used
+host_seconds 1775.41 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221363384 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 4899 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 266857181 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 74594 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 119571219 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 119976250 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 250511173 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3654 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 297137957 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 3218385 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012060 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 829150425 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 456900250 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 457303449 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 260922611 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4994873 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 4333463 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 4335295 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2397328 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 266351243 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2512979 # Number of floating point alu accesses
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 10:36:29
-gem5 started Jun 21 2014 10:37:19
+gem5 compiled Apr 22 2015 07:55:25
+gem5 started Apr 22 2015 08:11:59
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 21025000 because target called exit()
+Exiting @ tick 22074000 because target called exit()
sim_ticks 22074000 # Number of ticks simulated
final_tick 22074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 94896 # Simulator instruction rate (inst/s)
-host_op_rate 94876 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 328609283 # Simulator tick rate (ticks/s)
-host_mem_usage 293652 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 27311 # Simulator instruction rate (inst/s)
+host_op_rate 27309 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 94600483 # Simulator tick rate (ticks/s)
+host_mem_usage 225500 # Number of bytes of host memory used
+host_seconds 0.23 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 10742 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6197 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 6591 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3553 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 14185 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 146 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013592 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 35814 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 19169 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 19563 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 9787 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 19 2014 12:27:06
-gem5 started Jul 19 2014 12:27:28
+gem5 compiled Apr 22 2015 07:55:25
+gem5 started Apr 22 2015 08:43:58
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 11975500 because target called exit()
+Exiting @ tick 12774000 because target called exit()
sim_ticks 12774000 # Number of ticks simulated
final_tick 12774000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 77109 # Simulator instruction rate (inst/s)
-host_op_rate 77075 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 412290611 # Simulator tick rate (ticks/s)
-host_mem_usage 293132 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 38054 # Simulator instruction rate (inst/s)
+host_op_rate 38045 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 203548685 # Simulator tick rate (ticks/s)
+host_mem_usage 224448 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 3966 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 2151 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 2386 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1238 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 7337 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 58 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.014624 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 15337 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 6922 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 7157 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 3670 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.checker]
type=O3Checker
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
kvmInSE=false
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 11:25:19
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 14:33:28
gem5 executing on phenom
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
+
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.checker.isa: ISA system set to: 0 0x54ee6d0
- 0: system.cpu.isa: ISA system set to: 0 0x54ee6d0
+ 0: system.cpu.checker.isa: ISA system set to: 0 0x38f90a0
+ 0: system.cpu.isa: ISA system set to: 0 0x38f90a0
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 16786000 because target called exit()
+Exiting @ tick 17307500 because target called exit()
sim_ticks 17307500 # Number of ticks simulated
final_tick 17307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 56147 # Simulator instruction rate (inst/s)
-host_op_rate 65749 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 211593476 # Simulator tick rate (ticks/s)
-host_mem_usage 308560 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 36602 # Simulator instruction rate (inst/s)
+host_op_rate 42863 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 137949898 # Simulator tick rate (ticks/s)
+host_mem_usage 239992 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5377 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 8345 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4743 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 5005 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 12819 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 13520 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 169 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.020252 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 30336 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 15016 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 15278 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 7551 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
numThreads=1
-predType=bi-mode
[system.cpu.dcache]
type=BaseCache
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
+forward_snoops=false
hit_latency=1
is_top_level=true
max_miss_count=0
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
kvmInSE=false
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 11:25:21
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 11:26:41
gem5 executing on phenom
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x4e56660
+ 0: system.cpu.isa: ISA system set to: 0 0x4144ba0
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 16786000 because target called exit()
+Exiting @ tick 17911000 because target called exit()
sim_ticks 17911000 # Number of ticks simulated
final_tick 17911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 61363 # Simulator instruction rate (inst/s)
-host_op_rate 71855 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 239307903 # Simulator tick rate (ticks/s)
-host_mem_usage 305224 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 35404 # Simulator instruction rate (inst/s)
+host_op_rate 41460 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 138087840 # Simulator tick rate (ticks/s)
+host_mem_usage 236512 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5377 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 7136 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 186 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 2794 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 3002 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 7753 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 15493 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 1446 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.202635 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 31353 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 11164 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 11372 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 6550 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
kvmInSE=false
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff
-Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 10:59:13
-gem5 started Jun 21 2014 10:59:41
+gem5 compiled Apr 22 2015 07:56:24
+gem5 started Apr 22 2015 08:02:17
gem5 executing on phenom
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 21842500 because target called exit()
+Exiting @ tick 22762000 because target called exit()
sim_ticks 22762000 # Number of ticks simulated
final_tick 22762000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 85129 # Simulator instruction rate (inst/s)
-host_op_rate 85110 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 388456550 # Simulator tick rate (ticks/s)
-host_mem_usage 291584 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 3472 # Simulator instruction rate (inst/s)
+host_op_rate 3472 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 15849922 # Simulator tick rate (ticks/s)
+host_mem_usage 223436 # Number of bytes of host memory used
+host_seconds 1.44 # Real time elapsed on the host
sim_insts 4986 # Number of instructions simulated
sim_ops 4986 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 8204 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 35 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 3309 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 3964 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1790 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 14478 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 196 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.023891 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 31113 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 12267 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 12922 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 7408 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
kvmInSE=false
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simout
-Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:03:15
-gem5 started Jun 21 2014 11:03:43
+gem5 compiled Apr 22 2015 08:07:28
+gem5 started Apr 22 2015 08:13:52
gem5 executing on phenom
command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 19030500 because target called exit()
+Exiting @ tick 20101000 because target called exit()
sim_ticks 20101000 # Number of ticks simulated
final_tick 20101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 103196 # Simulator instruction rate (inst/s)
-host_op_rate 103171 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 357968408 # Simulator tick rate (ticks/s)
-host_mem_usage 289136 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 29548 # Simulator instruction rate (inst/s)
+host_op_rate 29545 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 102528509 # Simulator tick rate (ticks/s)
+host_mem_usage 221532 # Number of bytes of host memory used
+host_seconds 0.20 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 9105 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4184 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 4591 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3348 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 12714 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 252 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.027677 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 31189 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 14543 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 14945 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 8271 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 31 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 9323 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
eventq_index=0
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/x86/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
kvmInSE=false
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:13:07
-gem5 started Jun 21 2014 11:13:51
+gem5 compiled Apr 22 2015 08:10:29
+gem5 started Apr 22 2015 09:21:48
gem5 executing on phenom
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 19813000 because target called exit()
+Exiting @ tick 21143500 because target called exit()
sim_ticks 21143500 # Number of ticks simulated
final_tick 21143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 49814 # Simulator instruction rate (inst/s)
-host_op_rate 90238 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 195722405 # Simulator tick rate (ticks/s)
-host_mem_usage 309420 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 36086 # Simulator instruction rate (inst/s)
+host_op_rate 65370 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 141788196 # Simulator tick rate (ticks/s)
+host_mem_usage 241940 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 17882 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 11007 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 11697 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 16508 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 23838 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 223 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012471 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 59896 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 32462 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 33148 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 16353 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 18098 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=2
-predType=tournament
[system.cpu.dcache]
type=BaseCache
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 10:36:29
-gem5 started Jun 21 2014 10:38:01
+gem5 compiled Apr 22 2015 07:55:25
+gem5 started Apr 22 2015 08:18:53
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Hello world!
Hello world!
-Exiting @ tick 24521000 because target called exit()
+Exiting @ tick 25499500 because target called exit()
sim_ticks 25499500 # Number of ticks simulated
final_tick 25499500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 83845 # Simulator instruction rate (inst/s)
-host_op_rate 83838 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 167736694 # Simulator tick rate (ticks/s)
-host_mem_usage 294000 # Number of bytes of host memory used
-host_seconds 0.15 # Real time elapsed on the host
+host_inst_rate 60058 # Simulator instruction rate (inst/s)
+host_op_rate 60053 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 120151989 # Simulator tick rate (ticks/s)
+host_mem_usage 226048 # Number of bytes of host memory used
+host_seconds 0.21 # Real time elapsed on the host
sim_insts 12744 # Number of instructions simulated
sim_ops 12744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 22900 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 102 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 13893 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 14934 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 8231 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 27699 # Number of insts issued each cycle
system.cpu.iq.fu_busy_rate::1 0.007336 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::total 0.014323 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 73887 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 41585 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 42626 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 20089 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
kvmInSE=false
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:07:38
-gem5 started Jun 21 2014 11:08:19
+gem5 compiled Apr 22 2015 08:08:31
+gem5 started Apr 22 2015 08:14:03
gem5 executing on phenom
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Begining test of difficult SPARC instructions...
LDTW: Passed
STTW: Passed
Done
-Exiting @ tick 26706500 because target called exit()
+Exiting @ tick 27482500 because target called exit()
sim_ticks 27482500 # Number of ticks simulated
final_tick 27482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 86365 # Simulator instruction rate (inst/s)
-host_op_rate 86358 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 164391633 # Simulator tick rate (ticks/s)
-host_mem_usage 291648 # Number of bytes of host memory used
-host_seconds 0.17 # Real time elapsed on the host
+host_inst_rate 15220 # Simulator instruction rate (inst/s)
+host_op_rate 15220 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 28973949 # Simulator tick rate (ticks/s)
+host_mem_usage 223564 # Number of bytes of host memory used
+host_seconds 0.95 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.iq.iqNonSpecInstsAdded 726 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 21924 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 9151 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 9945 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 6501 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 251 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 32422 # Number of insts issued each cycle
system.cpu.iq.fu_busy_cnt 225 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010263 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 76549 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 33558 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 34352 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu0.dcache]
type=BaseCache
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
kvmInSE=false
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu1.dcache]
type=BaseCache
icache_port=system.cpu2.icache.cpu_side
[system.cpu2.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu2.dcache]
type=BaseCache
icache_port=system.cpu3.icache.cpu_side
[system.cpu3.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu3.dcache]
type=BaseCache
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 11 2014 05:01:31
-gem5 started Oct 11 2014 05:01:48
-gem5 executing on ribera.cs.wisc.edu
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+gem5 compiled Apr 22 2015 08:08:31
+gem5 started Apr 22 2015 08:17:28
+gem5 executing on phenom
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
-[Iteration 1, Thread 2] Got lock
-[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 1, Thread 1] Got lock
-[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 1, Thread 2] Got lock
+[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
Iteration 1 completed
[Iteration 2, Thread 2] Got lock
[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 2, Thread 1] Got lock
[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1
Iteration 2 completed
-[Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 3, Thread 1] Got lock
+[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2
Iteration 3 completed
[Iteration 4, Thread 2] Got lock
[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 5, Thread 3] Got lock
[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3
Iteration 5 completed
-[Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 6, Thread 1] Got lock
+[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 6, Thread 2] Got lock
+[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2
Iteration 6 completed
-[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 7, Thread 1] Got lock
[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 7, Thread 3] Got lock
+[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
Iteration 7 completed
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
Iteration 8 completed
-[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 9, Thread 1] Got lock
+[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3
Iteration 9 completed
-[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 10, Thread 1] Got lock
+[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2
Iteration 10 completed
PASSED :-)
-Exiting @ tick 105696000 because target called exit()
+Exiting @ tick 107944000 because target called exit()
sim_ticks 107944000 # Number of ticks simulated
final_tick 107944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 162812 # Simulator instruction rate (inst/s)
-host_op_rate 162812 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 17679745 # Simulator tick rate (ticks/s)
-host_mem_usage 308116 # Number of bytes of host memory used
-host_seconds 6.11 # Real time elapsed on the host
+host_inst_rate 128828 # Simulator instruction rate (inst/s)
+host_op_rate 128828 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 13989470 # Simulator tick rate (ticks/s)
+host_mem_usage 239356 # Number of bytes of host memory used
+host_seconds 7.72 # Real time elapsed on the host
sim_insts 994048 # Number of instructions simulated
sim_ops 994048 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.iq.iqNonSpecInstsAdded 967 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 386997 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 24 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 12329 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsExamined 13187 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 11208 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 408 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 189580 # Number of insts issued each cycle
system.cpu0.iq.fu_busy_cnt 278 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.000718 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 963876 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 403692 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_writes 404550 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 385100 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.iqNonSpecInstsAdded 6146 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 225009 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 16 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 12719 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedInstsExamined 13593 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 10743 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 680 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 156364 # Number of insts issued each cycle
system.cpu1.iq.fu_busy_cnt 330 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.001467 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 606728 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 242381 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_writes 243255 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 223369 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.iqNonSpecInstsAdded 6983 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 220497 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 13020 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedInstsExamined 13773 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 12313 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 622 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 159877 # Number of insts issued each cycle
system.cpu2.iq.fu_busy_cnt 363 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.001646 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 601287 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 238674 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_writes 239427 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 218768 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.iqNonSpecInstsAdded 7365 # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued 213102 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 12659 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedInstsExamined 13428 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined 11687 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved 617 # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples 159935 # Number of insts issued each cycle
system.cpu3.iq.fu_busy_cnt 350 # FU busy when requested
system.cpu3.iq.fu_busy_rate 0.001642 # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads 586529 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 230693 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_writes 231462 # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses 211399 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
projects / gem5.git / commitdiff