Connections between inputs and inouts are driven by the input

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 466808216458e4619076f184f49a3d0bb6533155..6600ffa25126ec72d425b3ff2e1d339abed0b6e5 100644 (file)
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -156,6 +156,9 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPoo
        if (w1->port_input != w2->port_input)
                return w2->port_input;
 
+       if ((w1->port_input && w1->port_output) != (w2->port_input && w2->port_output))
+               return !(w2->port_input && w2->port_output);
+
        if (w1->name[0] == '\\' && w2->name[0] == '\\') {
                if (regs.check_any(s1) != regs.check_any(s2))
                        return regs.check_any(s2);