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diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 38134e48a05f5a6c43de36b6c99de6f971b71927..7d8cddd1b8957889be1379124b65a80ade11f46a 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -223,6 +223,10 @@ than the normal 0..VL-1
 * **N** sets signed/unsigned saturation.
 **RC1** as if Rc=1, stores CRs *but not the result*
 
+For LD/ST Modes, see and [[sv/ldst]].  Immediate and Indexed LD/ST
+are both different, in order to support a large range of features
+normally found in Vector ISAs.
+
 # ELWIDTH Encoding
 
 Default behaviour is set to 0b00 so that zeros follow the convention of