radv: add explicit external subpass dependencies to meta operations

No functional changes because a subpass dependency with dstStageMask
set to VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT is a no-op.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3330>

diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c
index 16c5b93c093bb96883896116c2c1de017de77c5b..c19c1203db64f5f0c4992ee7b3e2c632ad15dbd3 100644 (file)
--- a/src/amd/vulkan/radv_meta_blit.c
+++ b/src/amd/vulkan/radv_meta_blit.c
@@ -959,7 +959,27 @@ radv_device_init_meta_blit_color(struct radv_device *device, bool on_demand)
                                                                .preserveAttachmentCount = 0,
                                                                .pPreserveAttachments = NULL,
                                                        },
-                                                       .dependencyCount = 0,
+                                                       .dependencyCount = 2,
+                                                       .pDependencies = (VkSubpassDependency[]) {
+                                                               {
+                                                                       .srcSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .dstSubpass = 0,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               },
+                                                               {
+                                                                       .srcSubpass = 0,
+                                                                       .dstSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               }
+                                                       },
                                                }, &device->meta_state.alloc, &device->meta_state.blit.render_pass[key][j]);
                        if (result != VK_SUCCESS)
                                goto fail;
@@ -1019,7 +1039,27 @@ radv_device_init_meta_blit_depth(struct radv_device *device, bool on_demand)
                                                               .preserveAttachmentCount = 0,
                                                               .pPreserveAttachments = NULL,
                                                        },
-                                                       .dependencyCount = 0,
+                                                       .dependencyCount = 2,
+                                                       .pDependencies = (VkSubpassDependency[]) {
+                                                               {
+                                                                       .srcSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .dstSubpass = 0,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               },
+                                                               {
+                                                                       .srcSubpass = 0,
+                                                                       .dstSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               }
+                                                       },
                                                }, &device->meta_state.alloc, &device->meta_state.blit.depth_only_rp[ds_layout]);
                if (result != VK_SUCCESS)
                        goto fail;
@@ -1076,7 +1116,28 @@ radv_device_init_meta_blit_stencil(struct radv_device *device, bool on_demand)
                                                               .preserveAttachmentCount = 0,
                                                               .pPreserveAttachments = NULL,
                                                       },
-                                                      .dependencyCount = 0,
+                                                      .dependencyCount = 2,
+                                                      .pDependencies = (VkSubpassDependency[]) {
+                                                               {
+                                                                       .srcSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .dstSubpass = 0,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               },
+                                                               {
+                                                                       .srcSubpass = 0,
+                                                                       .dstSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               }
+                                                       },
+
                                         }, &device->meta_state.alloc, &device->meta_state.blit.stencil_only_rp[ds_layout]);
        }
        if (result != VK_SUCCESS)

diff --git a/src/amd/vulkan/radv_meta_blit2d.c b/src/amd/vulkan/radv_meta_blit2d.c
index 819941bc8b2a62af7aaf6ba35e992efb541a77d3..06d95ceeab47fc453b4ec4c655de32a7c0bb2d6f 100644 (file)
--- a/src/amd/vulkan/radv_meta_blit2d.c
+++ b/src/amd/vulkan/radv_meta_blit2d.c
@@ -817,7 +817,27 @@ blit2d_init_color_pipeline(struct radv_device *device,
                                                .preserveAttachmentCount = 0,
                                                .pPreserveAttachments = NULL,
                                                },
-                                               .dependencyCount = 0,
+                                               .dependencyCount = 2,
+                                               .pDependencies = (VkSubpassDependency[]) {
+                                                       {
+                                                               .srcSubpass = VK_SUBPASS_EXTERNAL,
+                                                               .dstSubpass = 0,
+                                                               .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                               .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                               .srcAccessMask = 0,
+                                                               .dstAccessMask = 0,
+                                                               .dependencyFlags = 0
+                                                       },
+                                                       {
+                                                               .srcSubpass = 0,
+                                                               .dstSubpass = VK_SUBPASS_EXTERNAL,
+                                                               .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                               .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                               .srcAccessMask = 0,
+                                                               .dstAccessMask = 0,
+                                                               .dependencyFlags = 0
+                                                       }
+                                               },
                                        }, &device->meta_state.alloc, &device->meta_state.blit2d_render_passes[fs_key][dst_layout]);
                }
        }
@@ -988,7 +1008,27 @@ blit2d_init_depth_only_pipeline(struct radv_device *device,
                                                                       .preserveAttachmentCount = 0,
                                                                       .pPreserveAttachments = NULL,
                                                               },
-                                                              .dependencyCount = 0,
+                                                              .dependencyCount = 2,
+                                                              .pDependencies = (VkSubpassDependency[]) {
+                                                               {
+                                                                       .srcSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .dstSubpass = 0,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               },
+                                                               {
+                                                                       .srcSubpass = 0,
+                                                                       .dstSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               }
+                                                       },
                                                        }, &device->meta_state.alloc, &device->meta_state.blit2d_depth_only_rp[ds_layout]);
                }
        }
@@ -1158,7 +1198,27 @@ blit2d_init_stencil_only_pipeline(struct radv_device *device,
                                                                       .preserveAttachmentCount = 0,
                                                                       .pPreserveAttachments = NULL,
                                                               },
-                                                              .dependencyCount = 0,
+                                                              .dependencyCount = 2,
+                                                              .pDependencies = (VkSubpassDependency[]) {
+                                                               {
+                                                                       .srcSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .dstSubpass = 0,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               },
+                                                               {
+                                                                       .srcSubpass = 0,
+                                                                       .dstSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               }
+                                                       },
                                                       }, &device->meta_state.alloc, &device->meta_state.blit2d_stencil_only_rp[ds_layout]);
                }
        }

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index f57cbba68feb89d5253b86b2e17983bdc6755fcc..6a66665d06d4ad0f0b61478744dd9f42b5598596 100644 (file)
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -235,7 +235,27 @@ create_color_renderpass(struct radv_device *device,
                                                       .preserveAttachmentCount = 0,
                                                       .pPreserveAttachments = NULL,
                                               },
-                                                               .dependencyCount = 0,
+                                                       .dependencyCount = 2,
+                                                       .pDependencies = (VkSubpassDependency[]) {
+                                                               {
+                                                                       .srcSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .dstSubpass = 0,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               },
+                                                               {
+                                                                       .srcSubpass = 0,
+                                                                       .dstSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               }
+                                                       },
                                                                         }, &device->meta_state.alloc, pass);
        mtx_unlock(&device->meta_state.mtx);
        return result;
@@ -586,7 +606,27 @@ create_depthstencil_renderpass(struct radv_device *device,
                                                       .preserveAttachmentCount = 0,
                                                       .pPreserveAttachments = NULL,
                                               },
-                                                               .dependencyCount = 0,
+                                                       .dependencyCount = 2,
+                                                       .pDependencies = (VkSubpassDependency[]) {
+                                                               {
+                                                                       .srcSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .dstSubpass = 0,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               },
+                                                               {
+                                                                       .srcSubpass = 0,
+                                                                       .dstSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               }
+                                                       }
                                                                         }, &device->meta_state.alloc, render_pass);
        mtx_unlock(&device->meta_state.mtx);
        return result;
@@ -2084,7 +2124,28 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
                                              .pAttachments = &att_desc,
                                              .subpassCount = 1,
                                              .pSubpasses = &subpass_desc,
-                                             },
+                                             .dependencyCount = 2,
+                                             .pDependencies = (VkSubpassDependency[]) {
+                                                       {
+                                                               .srcSubpass = VK_SUBPASS_EXTERNAL,
+                                                               .dstSubpass = 0,
+                                                               .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                               .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                               .srcAccessMask = 0,
+                                                               .dstAccessMask = 0,
+                                                               .dependencyFlags = 0
+                                                       },
+                                                       {
+                                                               .srcSubpass = 0,
+                                                               .dstSubpass = VK_SUBPASS_EXTERNAL,
+                                                               .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                               .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                               .srcAccessMask = 0,
+                                                               .dstAccessMask = 0,
+                                                               .dependencyFlags = 0
+                                                       }
+                                               }
+                                       },
                              &cmd_buffer->pool->alloc,
                              &pass);
 

diff --git a/src/amd/vulkan/radv_meta_decompress.c b/src/amd/vulkan/radv_meta_decompress.c
index 3e6c6472018730ec3f31c2876538682191854dcd..d2cb3f089865c9fc12ecb77c7db6f11b12b97934 100644 (file)
--- a/src/amd/vulkan/radv_meta_decompress.c
+++ b/src/amd/vulkan/radv_meta_decompress.c
@@ -78,7 +78,27 @@ create_pass(struct radv_device *device,
                                                       .preserveAttachmentCount = 0,
                                                       .pPreserveAttachments = NULL,
                                               },
-                                                               .dependencyCount = 0,
+                                                       .dependencyCount = 2,
+                                                       .pDependencies = (VkSubpassDependency[]) {
+                                                               {
+                                                                       .srcSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .dstSubpass = 0,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               },
+                                                               {
+                                                                       .srcSubpass = 0,
+                                                                       .dstSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               }
+                                                       },
                                                                   },
                                       alloc,
                                       pass);

diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c
index 8e54c7286aa31192f42159602268afe1cb7abb72..84646a8b5dd8193da7faa7837a035840d6932412 100644 (file)
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -223,7 +223,27 @@ create_pass(struct radv_device *device)
                                                       .preserveAttachmentCount = 0,
                                                       .pPreserveAttachments = NULL,
                                               },
-                                                               .dependencyCount = 0,
+                                                       .dependencyCount = 2,
+                                                       .pDependencies = (VkSubpassDependency[]) {
+                                                               {
+                                                                       .srcSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .dstSubpass = 0,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               },
+                                                               {
+                                                                       .srcSubpass = 0,
+                                                                       .dstSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               }
+                                                       },
                                       },
                                       alloc,
                                       &device->meta_state.fast_clear_flush.pass);

diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c
index 8404a68ca1e3115ef6908681d1f9e203f7f40947..ed66a911284677033f1adff5f29d05ce4bab4d1a 100644 (file)
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -97,7 +97,27 @@ create_pass(struct radv_device *device, VkFormat vk_format, VkRenderPass *pass)
                                                       .preserveAttachmentCount = 0,
                                                       .pPreserveAttachments = NULL,
                                               },
-                                                               .dependencyCount = 0,
+                                                       .dependencyCount = 2,
+                                                       .pDependencies = (VkSubpassDependency[]) {
+                                                               {
+                                                                       .srcSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .dstSubpass = 0,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               },
+                                                               {
+                                                                       .srcSubpass = 0,
+                                                                       .dstSubpass = VK_SUBPASS_EXTERNAL,
+                                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                                       .srcAccessMask = 0,
+                                                                       .dstAccessMask = 0,
+                                                                       .dependencyFlags = 0
+                                                               }
+                                                       },
                                                                         },
                                       alloc,
                                       pass);

diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c b/src/amd/vulkan/radv_meta_resolve_fs.c
index 35a04c24a9b25c6c4a80d442f565308d9a87b478..2e8d40f04af24fb3c5b2158c75224a81b5d291a1 100644 (file)
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -231,7 +231,27 @@ create_resolve_pipeline(struct radv_device *device,
                                                .preserveAttachmentCount = 0,
                                                .pPreserveAttachments = NULL,
                                        },
-                                       .dependencyCount = 0,
+                                       .dependencyCount = 2,
+                                       .pDependencies = (VkSubpassDependency[]) {
+                                               {
+                                                       .srcSubpass = VK_SUBPASS_EXTERNAL,
+                                                       .dstSubpass = 0,
+                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                       .srcAccessMask = 0,
+                                                       .dstAccessMask = 0,
+                                                       .dependencyFlags = 0
+                                               },
+                                               {
+                                                       .srcSubpass = 0,
+                                                       .dstSubpass = VK_SUBPASS_EXTERNAL,
+                                                       .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                       .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                       .srcAccessMask = 0,
+                                                       .dstAccessMask = 0,
+                                                       .dependencyFlags = 0
+                                               }
+                                       },
                                }, &device->meta_state.alloc, rp + dst_layout);
        }
 
@@ -555,7 +575,27 @@ create_depth_stencil_resolve_pipeline(struct radv_device *device,
                                                        .preserveAttachmentCount = 0,
                                                        .pPreserveAttachments = NULL,
                                                },
-                                               .dependencyCount = 0,
+                                               .dependencyCount = 2,
+                                               .pDependencies = (VkSubpassDependency[]) {
+                                                       {
+                                                               .srcSubpass = VK_SUBPASS_EXTERNAL,
+                                                               .dstSubpass = 0,
+                                                               .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                               .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                               .srcAccessMask = 0,
+                                                               .dstAccessMask = 0,
+                                                               .dependencyFlags = 0
+                                                       },
+                                                       {
+                                                               .srcSubpass = 0,
+                                                               .dstSubpass = VK_SUBPASS_EXTERNAL,
+                                                               .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+                                                               .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+                                                               .srcAccessMask = 0,
+                                                               .dstAccessMask = 0,
+                                                               .dependencyFlags = 0
+                                                       }
+                                               },
                                        }, &device->meta_state.alloc, render_pass);
        }