litesata/core/link: move buffer on CONTInserter (seems better for timings when set...

diff --git a/misoclib/mem/litesata/core/link/__init__.py b/misoclib/mem/litesata/core/link/__init__.py
index a723112e4a190773a22ded7b396d0d567cf52ed4..f6553a0d9a6205db8dece929fa998c59d1c4386b 100644 (file)
--- a/misoclib/mem/litesata/core/link/__init__.py
+++ b/misoclib/mem/litesata/core/link/__init__.py
@@ -36,7 +36,7 @@ class LiteSATALinkTX(Module):
 
         # inserter CONT and scrambled data between
         # CONT and next primitive
-        cont = BufferizeEndpoints("source")(LiteSATACONTInserter(phy_description(32)))
+        cont = BufferizeEndpoints("sink")(LiteSATACONTInserter(phy_description(32)))
         self.submodules += cont
 
         # datas / primitives mux