i965: Set up the color masking for the first drawbuffer on gen6.

Fixes glean/maskedClear

diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index f51cf5f1120d4f6ecffd94723aa94ecfd0e11821..dfcef209618e9a7738973f37e2adc37e5e00b371 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -35,6 +35,7 @@
 struct gen6_blend_state_key {
    GLboolean color_blend, alpha_enabled;
    GLboolean dither;
+   GLboolean color_mask[4];
 
    GLenum logic_op;
 
@@ -53,6 +54,9 @@ blend_state_populate_key(struct brw_context *brw,
 
    memset(key, 0, sizeof(*key));
 
+   /* _NEW_COLOR */
+   memcpy(key->color_mask, ctx->Color.ColorMask[0], sizeof(key->color_mask));
+
    /* _NEW_COLOR */
    if (ctx->Color._LogicOpEnabled)
       key->logic_op = ctx->Color.LogicOp;
@@ -137,6 +141,11 @@ blend_state_create_from_key(struct brw_context *brw,
       blend.blend1.x_dither_offset = 0;
    }
 
+   blend.blend1.write_disable_r = !key->color_mask[0];
+   blend.blend1.write_disable_g = !key->color_mask[1];
+   blend.blend1.write_disable_b = !key->color_mask[2];
+   blend.blend1.write_disable_a = !key->color_mask[3];
+
    bo = brw_upload_cache(&brw->cache, BRW_BLEND_STATE,
                         key, sizeof(*key),
                         NULL, 0,