#define GEN6_MESSAGE_TARGET_DP_RENDER_CACHE 5
#define GEN6_MESSAGE_TARGET_DP_CONST_CACHE 9
+#define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10
+
#define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
#define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
#define BRW_SAMPLER_RETURN_FORMAT_SINT32 3
#define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13
#define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14
+/* GEN7 */
+#define GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 10
+
#define BRW_MATH_FUNCTION_INV 1
#define BRW_MATH_FUNCTION_LOG 2
#define BRW_MATH_FUNCTION_EXP 3
brw_set_src1(p, insn, brw_imm_ud(0));
if (intel->gen >= 7) {
+ /* Use the Render Cache for RT writes; otherwise use the Data Cache */
+ unsigned sfid = GEN7_MESSAGE_TARGET_DP_DATA_CACHE;
+ if (msg_type == GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE)
+ sfid = GEN6_MESSAGE_TARGET_DP_RENDER_CACHE;
+
+ insn->header.destreg__conditionalmod = sfid;
+
insn->bits3.gen7_dp.binding_table_index = binding_table_index;
insn->bits3.gen7_dp.msg_control = msg_control;
insn->bits3.gen7_dp.pixel_scoreboard_clear = pixel_scoreboard_clear;
insn->bits3.gen7_dp.response_length = response_length;
insn->bits3.gen7_dp.msg_length = msg_length;
insn->bits3.gen7_dp.end_of_thread = end_of_thread;
-
- /* We always use the render cache for write messages */
- insn->header.destreg__conditionalmod = GEN6_MESSAGE_TARGET_DP_RENDER_CACHE;
} else if (intel->gen == 6) {
insn->bits3.gen6_dp.binding_table_index = binding_table_index;
insn->bits3.gen6_dp.msg_control = msg_control;
insn->bits3.gen7_dp.response_length = response_length;
insn->bits3.gen7_dp.msg_length = msg_length;
insn->bits3.gen7_dp.end_of_thread = 0;
- insn->header.destreg__conditionalmod = GEN6_MESSAGE_TARGET_DP_CONST_CACHE;
+ insn->header.destreg__conditionalmod = GEN7_MESSAGE_TARGET_DP_DATA_CACHE;
} else if (intel->gen == 6) {
uint32_t target_function;