hierarchy - proc reorder

diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys
index 03aec66945b13fce7eaa22ae84c051148b59bf37..ee72d732f785ecbf77e6c3d7f7939bfef2ab0b96 100644 (file)
--- a/tests/ecp5/add_sub.ys
+++ b/tests/ecp5/add_sub.ys
@@ -1,5 +1,6 @@
 read_verilog add_sub.v
 hierarchy -top top
+proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module

diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys
index 658f302d001b2518403ea490df8dfe9db322ae1e..b129419d3bd4075cc2f02af9719fd2ed0bb9c53a 100644 (file)
--- a/tests/ecp5/adffs.ys
+++ b/tests/ecp5/adffs.ys
@@ -1,8 +1,8 @@
 read_verilog adffs.v
 design -save read
 
-proc
 hierarchy -top adff
+proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
@@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF
 select -assert-none t:TRELLIS_FF %% t:* %D
 
 design -load read
-proc
 hierarchy -top adffn
+proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
@@ -20,8 +20,8 @@ select -assert-count 1 t:LUT4
 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
 
 design -load read
-proc
 hierarchy -top dffs
+proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
@@ -30,8 +30,8 @@ select -assert-count 1 t:LUT4
 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
 
 design -load read
-proc
 hierarchy -top ndffnr
+proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module

diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys
index 93b8595adb22d6953e54c2bd60eb45078f0bb034..a4f45d2fb064b7af059eead1624c5bf343c36ef9 100644 (file)
--- a/tests/ecp5/dffs.ys
+++ b/tests/ecp5/dffs.ys
@@ -1,8 +1,8 @@
 read_verilog dffs.v
 design -save read
 
-proc
 hierarchy -top dff
+proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
@@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF
 select -assert-none t:TRELLIS_FF %% t:* %D
 
 design -load read
-proc
 hierarchy -top dffe
+proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module

diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys
index f329982326231fe6550a4ad60dac988845777f47..fc15a6910af59da5df76ade2c8fcfd843a52a169 100644 (file)
--- a/tests/ecp5/latches.ys
+++ b/tests/ecp5/latches.ys
@@ -2,8 +2,8 @@
 read_verilog latches.v
 design -save read
 
-proc
 hierarchy -top latchp
+proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
 synth_ecp5
 cd latchp # Constrain all select calls below inside the top module
@@ -13,8 +13,8 @@ select -assert-none t:LUT4 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top latchn
+proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
 synth_ecp5
 cd latchn # Constrain all select calls below inside the top module
@@ -24,8 +24,8 @@ select -assert-none t:LUT4 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top latchsr
+proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
 synth_ecp5
 cd latchsr # Constrain all select calls below inside the top module

diff --git a/tests/ecp5/logic.ys b/tests/ecp5/logic.ys
index 34125fea945aef0921fcfb4ced210baa973b6633..4f113a130708b04364f93291d61514ea3a7efe17 100644 (file)
--- a/tests/ecp5/logic.ys
+++ b/tests/ecp5/logic.ys
@@ -1,5 +1,6 @@
 read_verilog logic.v
 hierarchy -top top
+proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module

diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys
index f60281a54f0c0be88bd6e0c2b7e1951ba701df0e..1863ea4d2797f86221868e8f4a77bf539215df32 100644 (file)
--- a/tests/ecp5/macc.ys
+++ b/tests/ecp5/macc.ys
@@ -1,6 +1,6 @@
 read_verilog macc.v
-proc
 hierarchy -top top
+proc
 # Blocked by issue #1358 (Missing ECP5 simulation models)
 #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check

diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys
index 1323406645c142071e7433664fac3c0d23eb681f..0a91f892e75c30b1358a0e43568a7c608ebd7de6 100644 (file)
--- a/tests/ecp5/mul.ys
+++ b/tests/ecp5/mul.ys
@@ -1,5 +1,6 @@
 read_verilog mul.v
 hierarchy -top top
+proc
 # Blocked by issue #1358 (Missing ECP5 simulation models)
 #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check

diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys
index eada276bac24a2450f2b239fcc819a3964f42c7a..8cfbd541be9a06d6447d8fc8215675fb5978996e 100644 (file)
--- a/tests/ecp5/mux.ys
+++ b/tests/ecp5/mux.ys
@@ -1,8 +1,8 @@
 read_verilog mux.v
 design -save read
 
-proc
 hierarchy -top mux2
+proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
@@ -10,8 +10,8 @@ select -assert-count 1 t:LUT4
 select -assert-none t:LUT4 %% t:* %D
 
 design -load read
-proc
 hierarchy -top mux4
+proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
@@ -22,8 +22,8 @@ select -assert-count 2 t:PFUMX
 select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
 
 design -load read
-proc
 hierarchy -top mux8
+proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
@@ -34,8 +34,8 @@ select -assert-count 2 t:PFUMX
 select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
 
 design -load read
-proc
 hierarchy -top mux16
+proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module

diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys
index 8a52749a1f2b32abb14a0d03dd09912c603dd01e..98645ae4308a36a74fae3b6b96026f8a7e9c8f14 100644 (file)
--- a/tests/ecp5/rom.ys
+++ b/tests/ecp5/rom.ys
@@ -1,4 +1,5 @@
 read_verilog rom.v
+hierarchy -top top
 proc
 flatten
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check