gallium/r600: Replace ALIGN_DIVUP with DIV_ROUND_UP
authorKrzysztof Sobiecki <sobkas@gmail.com>
Tue, 29 Dec 2015 19:27:44 +0000 (20:27 +0100)
committerNicolai Hähnle <nicolai.haehnle@amd.com>
Wed, 6 Jan 2016 21:09:12 +0000 (16:09 -0500)
ALIGN_DIVUP is a driver specific(r600g) macro that duplicates DIV_ROUND_UP functionality.
Replacing it with DIV_ROUND_UP eliminates this problems.

Signed-off-by: Krzysztof A. Sobiecki <sobkas@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
src/gallium/drivers/r600/evergreen_state.c
src/gallium/drivers/r600/r600_pipe.h
src/gallium/drivers/r600/r600_state.c

index 1aee7dd2da8601ce19c4e19925705bd0d79d4632..9dfb84965cf980d7ab7c08eaaa1f0904bedbe4bb 100644 (file)
@@ -1956,7 +1956,7 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx,
 
                if (!gs_ring_buffer) {
                        radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
-                                                   ALIGN_DIVUP(cb->buffer_size, 256), pkt_flags);
+                                                   DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
                        radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
                                                    pkt_flags);
                }
index 31f2a729494fe2046f5f4bd9d010ae1b78475727..0e4dd16525be4a66a193bc6e81d599a0657bb242 100644 (file)
@@ -946,7 +946,6 @@ static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
 {
        return value * (1 << frac_bits);
 }
-#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 
 /* 12.4 fixed-point */
 static inline unsigned r600_pack_float_12p4(float x)
index 43b80742cb5c7b23f9c59690a14697341fa64fcb..f60e30486a2db9c187c6c318782ee3fcfaa86347 100644 (file)
@@ -1768,7 +1768,7 @@ static void r600_emit_constant_buffers(struct r600_context *rctx,
 
                if (!gs_ring_buffer) {
                        radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
-                                              ALIGN_DIVUP(cb->buffer_size, 256));
+                                              DIV_ROUND_UP(cb->buffer_size, 256));
                        radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
                }