copy README chapters to .rst

diff --git a/README b/README
index 63cc3f9ab6960918c8797b7b014c9b5e8f985c78..d0efbe0af5d1ef610edff65da5be1bd4961f8838 100644 (file)
--- a/README
+++ b/README
@@ -62,7 +62,7 @@ Frontend:
 
 [> Possibles improvements
 ----------------------
-- add standardized adapters (AXI, Avalon-ST)
+- add standardized interfaces (AXI, Avalon-ST)
 - add NCQ support
 - add AES hardware encryption
 - add on-the-flow compression/decompression

diff --git a/doc/source/docs/getting_started/downloads.rst b/doc/source/docs/getting_started/downloads.rst
index d799ee11b90f5857f19016c7e72d6ef1b012fc74..c906e555f0c2cbc8d4e45ab3cadef27c77ee54ba 100644 (file)
--- a/doc/source/docs/getting_started/downloads.rst
+++ b/doc/source/docs/getting_started/downloads.rst
@@ -3,3 +3,28 @@
 ====================
 Download and install
 ====================
+1. Install Python3 and Xilinx's Vivado software
+
+2. Obtain Migen and install it:
+  - git clone https://github.com/enjoy-digital/migen
+  - cd migen
+  - python3 setup.py install
+  - cd ..
+
+3. Obtain Miscope and install it:
+  - git clone https://github.com/enjoy-digital/miscope
+  - cd miscope
+  - python3 setup.py install
+  - cd ..
+
+4. Obtain MiSoC:
+  - git clone https://github.com/enjoy-digital/misoc --recursive
+
+5. Copy lite-sata in working directory and move to it.
+
+6. Build and load design:
+  - python3 make.py all
+
+7. Test design:
+  - go to test directory and run:
+  - python3 bist.py

diff --git a/doc/source/docs/getting_started/index.rst b/doc/source/docs/getting_started/index.rst
index 651b0251d3d2e43588ca896cc51a8e3e7d0316f7..e244ece79c66dc897b69d45e55405a8830663565 100644 (file)
--- a/doc/source/docs/getting_started/index.rst
+++ b/doc/source/docs/getting_started/index.rst
@@ -7,3 +7,10 @@ Getting Started
 Now you know why LiteSATA is :ref:`core for you <about-litesata>`, it's time to *get started*.
 
 This section provides a walk-through of :ref:`downloading and installing the tools`.
+
+.. toctree::
+       :maxdepth: 1
+
+       downloads
+       FAQ
+

diff --git a/doc/source/docs/introducing_litesata/about_litesata.rst b/doc/source/docs/introducing_litesata/about_litesata.rst
index 95ad19d17da24f777b15c2ac8996a6aaa5881543..30183161bec2266856ad162935b054f9af3d865a 100644 (file)
--- a/doc/source/docs/introducing_litesata/about_litesata.rst
+++ b/doc/source/docs/introducing_litesata/about_litesata.rst
@@ -55,3 +55,18 @@ Frontend:
   - Configurable crossbar (simply use core.crossbar.get_port() to add a new port!)
   - Ports arbitration transparent to the user
   - Synthetizable BIST
+
+
+Possibles improvements
+====================
+- add standardized interfaces (AXI, Avalon-ST)
+- add NCQ support
+- add AES hardware encryption
+- add on-the-flow compression/decompression
+- add support for Altera PHYs.
+- add support for Lattice PHYs.
+- add support for Xilinx 7-Series GTP/GTH (currently only 7-Series GTX are
+  supported)
+- add Zynq Linux drivers.
+- ...
+

diff --git a/doc/source/docs/introducing_litesata/litesata_license.rst b/doc/source/docs/introducing_litesata/litesata_license.rst
index 2441335f01545caf8ac7e94546c87536580867f0..b56310d6eff95a1e769dc2c89e9f22de9de3494b 100644 (file)
--- a/doc/source/docs/introducing_litesata/litesata_license.rst
+++ b/doc/source/docs/introducing_litesata/litesata_license.rst
@@ -4,3 +4,13 @@
 Open Source License
 ===================
 
+LiteSATA is released under the very permissive two-clause BSD license. Under the
+terms of this license, you are authorized to use Migen for closed-source
+proprietary designs.
+Even though we do not require you to do so, those things are awesome, so please
+do them if possible:
+ - tell us that you are using LiteSATA
+ - cite Migen in publications related to research it has helped
+ - send us feedback and suggestions for improvements
+ - send us bug reports when something goes wrong
+ - send us the modifications and improvements you have done to LiteSATA.
\ No newline at end of file

diff --git a/doc/source/docs/simulation/index.rst b/doc/source/docs/simulation/index.rst
index 5f067b31ff79dc7fa2c8240025f5525f22e43882..7f29dd5b8e66e888775003688cd1063a1efd505b 100644 (file)
--- a/doc/source/docs/simulation/index.rst
+++ b/doc/source/docs/simulation/index.rst
@@ -3,3 +3,15 @@
 ========================
 Simulation
 ========================
+
+Simulations are avalaible in ./lib/sata/test:
+  - crc_tb
+  - scrambler_tb
+  - phy_datapath_tb
+  - link_tb
+  - command_tb
+  - bist_tb
+
+hdd.py is a simplified HDD model implementing all SATA layers.
+To run a simulation, move to ./lib/sata/test and run:
+  - make simulation_name
\ No newline at end of file

diff --git a/doc/source/docs/test/index.rst b/doc/source/docs/test/index.rst
index fee22dff910bcff5cf4f2b7b9b7f07624aa6acdb..b9dbf0aacb2b1de4a3bb18c170b8f475fa14d8d4 100644 (file)
--- a/doc/source/docs/test/index.rst
+++ b/doc/source/docs/test/index.rst
@@ -3,3 +3,8 @@
 ========================
 Test
 ========================
+
+A synthetisable BIST is provided and can be controlled with ./test/bist.py.
+By using Miscope and the provided ./test/test_link.py example you are able to
+visualize the internal logic of the design and even inject the captured data in
+the HDD model!
\ No newline at end of file