gallium/radeon: remove VPORT_ZMIN/ZMAX from init config states
authorMarek Olšák <marek.olsak@amd.com>
Fri, 26 Aug 2016 16:08:03 +0000 (18:08 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Mon, 5 Sep 2016 16:01:15 +0000 (18:01 +0200)
It's part of the viewport state now.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
src/gallium/drivers/r600/evergreen_state.c
src/gallium/drivers/r600/r600_state.c
src/gallium/drivers/radeonsi/si_state.c

index 5ca5453a8d7547e3bb6484cfbdccf2c038d06555..ed385ee9dcec1a0e529b7c2ca74fd44d92a63bc4 100644 (file)
@@ -2330,7 +2330,7 @@ void cayman_init_common_regs(struct r600_command_buffer *cb,
 static void cayman_init_atom_start_cs(struct r600_context *rctx)
 {
        struct r600_command_buffer *cb = &rctx->start_cs_cmd;
-       int tmp, i;
+       int i;
 
        r600_init_command_buffer(cb, 338);
 
@@ -2422,12 +2422,6 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx)
        r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
        r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
 
-       r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
-       for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
-               r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
-               r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
-       }
-
        r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
        r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
 
@@ -2832,12 +2826,6 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx)
        r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
        r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
 
-       r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
-       for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
-               r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
-               r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
-       }
-
        r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
        r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
 
index c8768e0343a9d2cf1e3bf165161fee55972737c6..c55c5322bfed78ded716348ec954246f18f5845c 100644 (file)
@@ -2374,12 +2374,6 @@ void r600_init_atom_start_cs(struct r600_context *rctx)
        r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
        r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
 
-       r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
-       for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
-               r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
-               r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
-       }
-
        r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
        r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
 
index 60ba3f6e8b32cd141fa20858618b697ead73cb56..280a9f88be5690f14f7221249b3052c9174125f3 100644 (file)
@@ -3760,7 +3760,6 @@ static void si_init_config(struct si_context *sctx)
        unsigned raster_config, raster_config_1;
        uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
        struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
-       int i;
 
        if (!pm4)
                return;
@@ -3792,11 +3791,6 @@ static void si_init_config(struct si_context *sctx)
 
        si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
 
-       for (i = 0; i < 16; i++) {
-               si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
-               si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
-       }
-
        switch (sctx->screen->b.family) {
        case CHIP_TAHITI:
        case CHIP_PITCAIRN: