Fixed the help summary line for a few commands

diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc
index 6094f8f16aedb8806096a2303596191df0a7e563..d09ed872ebc6ff9379df2dd1a9244c059e92ac77 100644 (file)
--- a/passes/cmds/blackbox.cc
+++ b/passes/cmds/blackbox.cc
@@ -23,7 +23,7 @@ USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
 struct BlackboxPass : public Pass {
-       BlackboxPass() : Pass("blackbox", "change type of cells in the design") { }
+       BlackboxPass() : Pass("blackbox", "convert modules into blackbox modules") { }
        void help() YS_OVERRIDE
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|

diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc
index 509cb0ba9df3be382e166c92d07448b88d3c6755..3b432c461a89fe484e80e89701c6e74a0b12ee6e 100644 (file)
--- a/passes/sat/assertpmux.cc
+++ b/passes/sat/assertpmux.cc
@@ -180,7 +180,7 @@ struct AssertpmuxWorker
 };
 
 struct AssertpmuxPass : public Pass {
-       AssertpmuxPass() : Pass("assertpmux", "convert internal signals to module ports") { }
+       AssertpmuxPass() : Pass("assertpmux", "adds asserts for parallel muxes") { }
        void help() YS_OVERRIDE
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@@ -195,8 +195,8 @@ struct AssertpmuxPass : public Pass {
                log("\n");
                log("    -always\n");
                log("        usually the $pmux condition is only checked when the $pmux output\n");
-               log("        is used be the mux tree it drives. this option will deactivate this\n");
-               log("        additional constrained and check the $pmux condition always.\n");
+               log("        is used by the mux tree it drives. this option will deactivate this\n");
+               log("        additional constraint and check the $pmux condition always.\n");
                log("\n");
        }
        void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE

diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc
index 048aec7f3436464c919073445fc511e085d31f21..b4549bc39b1630193a338c017d8c0156e6a05b0b 100644 (file)
--- a/passes/sat/cutpoint.cc
+++ b/passes/sat/cutpoint.cc
@@ -24,7 +24,7 @@ USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
 struct CutpointPass : public Pass {
-       CutpointPass() : Pass("cutpoint", "add hi/lo cover cells for each wire bit") { }
+       CutpointPass() : Pass("cutpoint", "adds formal cut points to the design") { }
        void help() YS_OVERRIDE
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|

diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
index 2428a8e7857a78cdc32b5d7fbaa1032182e2e361..bec3c4c9600f11ea8e2d59bf8149ed37c3af5f21 100644 (file)
--- a/techlibs/ice40/ice40_unlut.cc
+++ b/techlibs/ice40/ice40_unlut.cc
@@ -74,7 +74,7 @@ static void run_ice40_unlut(Module *module)
 }
 
 struct Ice40UnlutPass : public Pass {
-       Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: perform simple optimizations") { }
+       Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SBLUT4 cells to $lut cells") { }
        void help() YS_OVERRIDE
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|