PowerPC64 .branch_lt address

.branch_lt is really an extension of .plt, as is .iplt.  We'd like all
of the PLT sections to be fixed relative to .TOC. after stub sizing,
because changes in offset to PLT entries might mean a change in stub
sizes.  When -z relro, the relro layout does this by laying out
sections from the end of the relro segment.  So for example, a change
in .eh_frame (which happens after stub sizing) will keep the same GOT
to PLT offset when -z relro.  Not so when -z norelro, because then the
usual forward layout of section is done and .got is more aligned than
.branch_lt.

	* emulparams/elf64ppc.sh: Set .branch_lt address fixed relative
	to .got.
	* testsuite/ld-powerpc/elfv2exe.d: Adjust to suit.

diff --git a/ld/emulparams/elf64ppc.sh b/ld/emulparams/elf64ppc.sh
index a18393b7202f441bc87c5828ffb232db826812f6..59132fa06faf09f399e62d59fede18eb7fa83061 100644 (file)
--- a/ld/emulparams/elf64ppc.sh
+++ b/ld/emulparams/elf64ppc.sh
@@ -37,7 +37,7 @@ OTHER_GOT_RELOC_SECTIONS="
 OTHER_RELRO_SECTIONS_2="
   .opd         ${RELOCATING-0} :${RELOCATING+ ALIGN(8)} { KEEP (*(.opd)) }
   .toc1                ${RELOCATING-0} :${RELOCATING+ ALIGN(8)} { *(.toc1) }
-  .branch_lt   ${RELOCATING-0} :${RELOCATING+ ALIGN(8)} { *(.branch_lt) }"
+  .branch_lt   ${RELOCATING-0}${RELOCATING+(SIZEOF(.got) != 0 ? . + 255 - (255 & (. - 1 + ALIGN(SIZEOF(.branch_lt),8)${RELRO_NOW+ + ALIGN(SIZEOF(.plt),8) + ALIGN(SIZEOF(.iplt),8)})) : ALIGN(8))} : { *(.branch_lt) }"
 INITIAL_READWRITE_SECTIONS="
   .toc         ${RELOCATING-0} :${RELOCATING+ ALIGN(8)} { *(.toc) }"
 # Put .got before .data

diff --git a/ld/testsuite/ld-powerpc/elfv2exe.d b/ld/testsuite/ld-powerpc/elfv2exe.d
index 0ccfcbf345a64caf8efdc627ef9b9d1632aa2f54..586264d449bf6dc4753b3eea07bd2a9d831b5b0b 100644 (file)
--- a/ld/testsuite/ld-powerpc/elfv2exe.d
+++ b/ld/testsuite/ld-powerpc/elfv2exe.d
@@ -9,13 +9,13 @@ Disassembly of section \.text:
 
 0+100000c0 <.*\.plt_branch\.f4>:
 .*:    (3d 82 ff ff|ff ff 82 3d)       addis   r12,r2,-1
-.*:    (e9 8c 7f 58|58 7f 8c e9)       ld      r12,32600\(r12\)
+.*:    (e9 8c 7f f0|f0 7f 8c e9)       ld      r12,32752\(r12\)
 .*:    (7d 89 03 a6|a6 03 89 7d)       mtctr   r12
 .*:    (4e 80 04 20|20 04 80 4e)       bctr
 
 0+100000d0 <.*\.plt_branch\.f2>:
 .*:    (3d 82 ff ff|ff ff 82 3d)       addis   r12,r2,-1
-.*:    (e9 8c 7f 60|60 7f 8c e9)       ld      r12,32608\(r12\)
+.*:    (e9 8c 7f f8|f8 7f 8c e9)       ld      r12,32760\(r12\)
 .*:    (7d 89 03 a6|a6 03 89 7d)       mtctr   r12
 .*:    (4e 80 04 20|20 04 80 4e)       bctr