i965: Avoid blocking on the GPU for setting the HiZ op vertex data.

We need to allocate new space every time to avoid blocking on the last
HiZ op completing.  There are two easy ways to do this:
brw_state_batch() and intel_upload_data().  brw_state_batch() is
simpler and avoids another buffer allocation.

Improves Unigine Tropics performance 0.376416% +/- 0.148722% (n=7).

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 09d8373a1a18ebf590e290df3a946b2ea4885493..a16145b9baa2aa16068dbaee1f164d87f296e8dc 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -985,21 +985,6 @@ struct brw_context
    } *state_batch_list;
    int state_batch_count;
 
-   /**
-    * \brief State needed to execute HiZ ops.
-    *
-    * \see gen6_hiz_init()
-    * \see gen6_hiz_exec()
-    */
-   struct brw_hiz_state {
-      /** \brief VBO for rectangle primitive.
-       *
-       * Rather than using glGenBuffers(), we allocate the VBO directly
-       * through drm.
-       */
-      drm_intel_bo *vertex_bo;
-   } hiz;
-
    struct brw_sol_state {
       uint32_t svbi_0_starting_index;
       uint32_t svbi_0_max_index;

diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 724111c3dfecb536c7ec71bf57473cc60dd6661f..5e7345648db77af86b79b02a51326bf5a809780e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -75,7 +75,6 @@ static void brw_destroy_context( struct intel_context *intel )
    ralloc_free(brw->wm.compile_data);
 
    dri_bo_release(&brw->curbe.curbe_bo);
-   dri_bo_release(&brw->hiz.vertex_bo);
    dri_bo_release(&brw->vs.const_bo);
    dri_bo_release(&brw->wm.const_bo);
 

diff --git a/src/mesa/drivers/dri/i965/gen6_hiz.c b/src/mesa/drivers/dri/i965/gen6_hiz.c
index a86c14717b1c6be4a4a05f882e262de42b0037c9..9837b1fc54df818f4a300ca2896eb136e59d97a3 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_hiz.c
+++ b/src/mesa/drivers/dri/i965/gen6_hiz.c
@@ -46,27 +46,6 @@
                            * sizeof(float))
 /** \} */
 
-/**
- * \brief Initialize data needed for the HiZ op.
- *
- * This called when executing the first HiZ op.
- * \see brw_context::hiz
- */
-void
-gen6_hiz_init(struct brw_context *brw)
-{
-   struct gl_context *ctx = &brw->intel.ctx;
-   struct intel_context *intel = &brw->intel;
-   struct brw_hiz_state *hiz = &brw->hiz;
-
-   hiz->vertex_bo = drm_intel_bo_alloc(intel->bufmgr, "bufferobj",
-                                       GEN6_HIZ_VBO_SIZE, /* size */
-                                       64); /* alignment */
-
-   if (!hiz->vertex_bo)
-      _mesa_error(ctx, GL_OUT_OF_MEMORY, "failed to allocate internal VBO");
-}
-
 void
 gen6_hiz_emit_batch_head(struct brw_context *brw)
 {
@@ -156,7 +135,7 @@ gen6_hiz_emit_vertices(struct brw_context *brw,
                        unsigned int layer)
 {
    struct intel_context *intel = &brw->intel;
-   struct brw_hiz_state *hiz = &brw->hiz;
+   uint32_t vertex_offset;
 
    /* Setup VBO for the rectangle primitive..
     *
@@ -190,6 +169,7 @@ gen6_hiz_emit_vertices(struct brw_context *brw,
    {
       const int width = mt->level[level].width;
       const int height = mt->level[level].height;
+      float *vertex_data;
 
       const float vertices[GEN6_HIZ_VBO_SIZE] = {
          /* v0 */ 0, 0, 0, 0,         0, height, 0, 1,
@@ -197,7 +177,9 @@ gen6_hiz_emit_vertices(struct brw_context *brw,
          /* v2 */ 0, 0, 0, 0,         0,      0, 0, 1,
       };
 
-      drm_intel_bo_subdata(hiz->vertex_bo, 0, GEN6_HIZ_VBO_SIZE, vertices);
+      vertex_data = brw_state_batch(brw, AUB_TRACE_NO_TYPE,
+                                   GEN6_HIZ_VBO_SIZE, 32, &vertex_offset);
+      memcpy(vertex_data, vertices, GEN6_HIZ_VBO_SIZE);
    }
 
    /* 3DSTATE_VERTEX_BUFFERS */
@@ -215,10 +197,11 @@ gen6_hiz_emit_vertices(struct brw_context *brw,
       OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2));
       OUT_BATCH(dw0);
       /* start address */
-      OUT_RELOC(hiz->vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
+      OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
+               vertex_offset);
       /* end address */
-      OUT_RELOC(hiz->vertex_bo, I915_GEM_DOMAIN_VERTEX,
-                0, hiz->vertex_bo->size - 1);
+      OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
+               vertex_offset + GEN6_HIZ_VBO_SIZE - 1);
       OUT_BATCH(0);
       ADVANCE_BATCH();
    }
@@ -278,20 +261,11 @@ gen6_hiz_exec(struct intel_context *intel,
 {
    struct gl_context *ctx = &intel->ctx;
    struct brw_context *brw = brw_context(ctx);
-   struct brw_hiz_state *hiz = &brw->hiz;
 
    assert(op != GEN6_HIZ_OP_DEPTH_CLEAR); /* Not implemented yet. */
    assert(mt->hiz_mt != NULL);
    intel_miptree_check_level_layer(mt, level, layer);
 
-   if (hiz->vertex_bo == NULL)
-      gen6_hiz_init(brw);
-
-   if (hiz->vertex_bo == NULL) {
-      /* Ouch. Give up. */
-      return;
-   }
-
    gen6_hiz_emit_batch_head(brw);
    gen6_hiz_emit_vertices(brw, mt, level, layer);
 

diff --git a/src/mesa/drivers/dri/i965/gen7_hiz.c b/src/mesa/drivers/dri/i965/gen7_hiz.c
index 34e51ab4b5027183a43cbb3582a4595bd81cc277..50c265ece9b7ce61376f2fdac62ccbe53f312f25 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_hiz.c
+++ b/src/mesa/drivers/dri/i965/gen7_hiz.c
@@ -46,20 +46,11 @@ gen7_hiz_exec(struct intel_context *intel,
 {
    struct gl_context *ctx = &intel->ctx;
    struct brw_context *brw = brw_context(ctx);
-   struct brw_hiz_state *hiz = &brw->hiz;
 
    assert(op != GEN6_HIZ_OP_DEPTH_CLEAR); /* Not implemented yet. */
    assert(mt->hiz_mt != NULL);
    intel_miptree_check_level_layer(mt, level, layer);
 
-   if (hiz->vertex_bo == NULL)
-      gen6_hiz_init(brw);
-
-   if (hiz->vertex_bo == NULL) {
-      /* Ouch. Give up. */
-      return;
-   }
-
    uint32_t depth_format;
    switch (mt->format) {
    case MESA_FORMAT_Z16:       depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;