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diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index 23f87d234f967a832cb59f49f8f451a7020d6169..9acc60cd7bc70dcfaa1247ea1f3fbb2cd42c550c 100644 (file)
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -560,11 +560,23 @@ tight space, the encoding mode is *not* included in the prefix itself.
 The mode is "applied", similar to Power ISA "Forms" (X-Form, D-Form)
 on a per-instruction basis, and, like "Forms" are given a designation
 (below) of the form `RM-nP-nSnD`. The full list of which instructions
-use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV
-files have been provided which will make the task of creating SV-aware
-ISA decoders easier*).
+use which remaps is here [[opcode_regs_deduped]].
 
-These mappings are part of the SVP64 Specification in exactly the same
+**Please note the following**:
+
+```
+    Machine-readable CSV files have been provided which will make the task
+    of creating SV-aware ISA decoders, documentation, assembler tools
+    compiler tools Simulators documentation all aspects of SVP64 easier
+    and less prone to mistakes.  Please avoid manual re-creation of
+    information from the written specification wording, and use the
+    CSV files or use the Canonical tool which creates the CSV files,
+    named sv_analysis.py. The information contained within sv_analysis.py
+    is considered to be part of this Specification, even encoded as it
+    is in python3.
+```
+
+The mappings are part of the SVP64 Specification in exactly the same
 way as X-Form, D-Form. New Scalar instructions added to the Power ISA
 will need a corresponding SVP64 Mapping, which can be derived by-rote
 from examining the Register "Profile" of the instruction.