* archures.c: Add bfd_mach_ppc_e500mc64.
* bfd-in2.h: Regenerate.
* cpu-powerpc.c (bfd_powerpc_archs): Add entry for
bfd_mach_ppc_e500mc64.
gas/
* config/tc-ppc.c (md_show_usage): Document -me500mc64.
opcodes/
* ppc-dis.c (ppc_opts): Add entry for "e500mc64".
+2010-01-04 Edmar Wienskoski <edmar@freescale.com>
+
+ * archures.c: Add bfd_mach_ppc_e500mc64.
+ * bfd-in2.h: Regenerate.
+ * cpu-powerpc.c (bfd_powerpc_archs): Add entry for
+ bfd_mach_ppc_e500mc64.
+
2010-01-01 Joel Brobecker <brobecker@adacore.com>
Fix -Wshadow warnings (seen on ppc-aix)
/* BFD library support routines for architectures.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
Free Software Foundation, Inc.
Hacked by John Gilmore and Steve Chamberlain of Cygnus Support.
.#define bfd_mach_ppc_7400 7400
.#define bfd_mach_ppc_e500 500
.#define bfd_mach_ppc_e500mc 5001
+.#define bfd_mach_ppc_e500mc64 5005
. bfd_arch_rs6000, {* IBM RS/6000 *}
.#define bfd_mach_rs6k 6000
.#define bfd_mach_rs6k_rs1 6001
#define bfd_mach_ppc_7400 7400
#define bfd_mach_ppc_e500 500
#define bfd_mach_ppc_e500mc 5001
+#define bfd_mach_ppc_e500mc64 5005
bfd_arch_rs6000, /* IBM RS/6000 */
#define bfd_mach_rs6k 6000
#define bfd_mach_rs6k_rs1 6001
/* BFD PowerPC CPU definition
- Copyright 1994, 1995, 1996, 2000, 2001, 2002, 2003, 2005, 2007, 2008
+ Copyright 1994, 1995, 1996, 2000, 2001, 2002, 2003, 2005, 2007, 2008, 2010
Free Software Foundation, Inc.
Contributed by Ian Lance Taylor, Cygnus Support.
bfd_default_scan,
&bfd_powerpc_archs[15]
},
+ {
+ 64, /* 64 bits in a word */
+ 64, /* 64 bits in an address */
+ 8, /* 8 bits in a byte */
+ bfd_arch_powerpc,
+ bfd_mach_ppc_e500mc64,
+ "powerpc",
+ "powerpc:e500mc64",
+ 3,
+ FALSE, /* not the default */
+ powerpc_compatible,
+ bfd_default_scan,
+ &bfd_powerpc_archs[16]
+ },
{
32, /* 32 bits in a word */
32, /* 32 bits in an address */
FALSE, /* not the default */
powerpc_compatible,
bfd_default_scan,
- &bfd_powerpc_archs[16]
+ &bfd_powerpc_archs[17]
},
{
32, /* 32 bits in a word */
+2010-01-04 Edmar Wienskoski <edmar@freescale.com>
+
+ * config/tc-ppc.c (md_show_usage): Document -me500mc64.
+
2010-01-03 Daniel Gutson <dgutson@codesourcery.com>
* config/tc-arm.c (struct arm_it): New flag 'is_neon'.
(do_neon_cvt): Likewise.
(do_neon_mvn): Likewise.
(do_neon_dup): Likewise.
- (md_assemble): Call check_neon_suffixes ().
+ (md_assemble): Call check_neon_suffixes ().
For older changes see ChangeLog-2009
\f
/* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
- 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
+ 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support.
This file is part of GAS, the GNU Assembler.
-mvsx generate code for Vector-Scalar (VSX) instructions\n\
-me300 generate code for PowerPC e300 family\n\
-me500, -me500x2 generate code for Motorola e500 core complex\n\
--me500mc, generate code for Freescale e500mc core complex\n\
+-me500mc, generate code for Freescale e500mc core complex\n\
+-me500mc64, generate code for Freescale e500mc64 core complex\n\
-mspe generate code for Motorola SPE instructions\n\
-mregnames Allow symbolic names for registers\n\
-mno-regnames Do not allow symbolic names for registers\n"));
+2010-01-04 Edmar Wienskoski <edmar@freescale.com>
+
+ * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
+
2010-01-02 Doug Evans <dje@sebabeach.org>
* cgen-asm.in: Update copyright year.
/* ppc-dis.c -- Disassemble PowerPC instructions
Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
- 2008, 2009 Free Software Foundation, Inc.
+ 2008, 2009, 2010 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of the GNU opcodes library.
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
| PPC_OPCODE_E500MC),
0 },
+ { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+ | PPC_OPCODE_64 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+ | PPC_OPCODE_POWER7),
+ 0 },
{ "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI