radeonsi: clean up decompress flags in fast color clear

diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 520e5b94f4a6b49d78387ba56818a2de7e0efe0d..8aa3355afc8f8e9d28fcdbcdeb1e560bfcbf4a75 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -432,8 +432,6 @@ static void si_do_fast_color_clear(struct si_context *sctx,
                    !sctx->screen->info.htile_cmask_support_1d_tiling)
                        continue;
 
-               bool need_decompress_pass = false;
-
                /* Use a slow clear for small surfaces where the cost of
                 * the eliminate pass can be higher than the benefit of fast
                 * clear. The closed driver does this, but the numbers may differ.
@@ -443,6 +441,8 @@ static void si_do_fast_color_clear(struct si_context *sctx,
                bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
                                 tex->buffer.b.b.width0 *
                                 tex->buffer.b.b.height0 <= 512 * 512;
+               bool eliminate_needed = false;
+               bool fmask_decompress_needed = false;
 
                /* Fast clear is the most appropriate place to enable DCC for
                 * displayable surfaces.
@@ -462,7 +462,6 @@ static void si_do_fast_color_clear(struct si_context *sctx,
                /* Try to clear DCC first, otherwise try CMASK. */
                if (vi_dcc_enabled(tex, 0)) {
                        uint32_t reset_value;
-                       bool eliminate_needed;
 
                        if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
                                continue;
@@ -491,14 +490,10 @@ static void si_do_fast_color_clear(struct si_context *sctx,
                                si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
                                                tex->cmask_offset, tex->surface.cmask_size,
                                                &clear_value, 4, SI_COHERENCY_CB_META);
-                               need_decompress_pass = true;
+                               fmask_decompress_needed = true;
                        }
 
                        vi_dcc_clear_level(sctx, tex, 0, reset_value);
-
-                       if (eliminate_needed)
-                               need_decompress_pass = true;
-
                        tex->separate_dcc_dirty = true;
                } else {
                        if (too_small)
@@ -523,10 +518,10 @@ static void si_do_fast_color_clear(struct si_context *sctx,
                        si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
                                        tex->cmask_offset, tex->surface.cmask_size,
                                        &clear_value, 4, SI_COHERENCY_CB_META);
-                       need_decompress_pass = true;
+                       eliminate_needed = true;
                }
 
-               if (need_decompress_pass &&
+               if ((eliminate_needed || fmask_decompress_needed) &&
                    !(tex->dirty_level_mask & (1 << level))) {
                        tex->dirty_level_mask |= 1 << level;
                        p_atomic_inc(&sctx->screen->compressed_colortex_counter);
@@ -535,11 +530,12 @@ static void si_do_fast_color_clear(struct si_context *sctx,
                /* We can change the micro tile mode before a full clear. */
                si_set_optimal_micro_tile_mode(sctx->screen, tex);
 
+               *buffers &= ~clear_bit;
+
                if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
                        sctx->framebuffer.dirty_cbufs |= 1 << i;
                        si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
                }
-               *buffers &= ~clear_bit;
        }
 }