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radeon/llvm: Add register encoding for VCC
authorTom Stellard <thomas.stellard@amd.com>
Wed, 5 Sep 2012 18:35:21 +0000 (14:35 -0400)
committerTom Stellard <thomas.stellard@amd.com>
Tue, 11 Sep 2012 18:53:47 +0000 (14:53 -0400)
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp patch | blob | history

diff --git a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
index 438d2acf989bbedb730fc3e9fc9a96a68238989d..ca4b579dcceffe52f8f5dfc874857360fc268357 100644 (file)
--- a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -280,6 +280,7 @@ unsigned SIMCCodeEmitter::getEncodingBytes(const MCInst &MI) const {
 
 unsigned SIMCCodeEmitter::getRegBinaryCode(unsigned reg) const {
   switch (reg) {
+    case AMDGPU::VCC: return 106;
     case AMDGPU::M0: return 124;
     case AMDGPU::EXEC: return 126;
     case AMDGPU::EXEC_LO: return 126;