freedreno/a6xx: Document dual-src blending enable bits

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5039>

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index a831ccc845d57352fdb96f81f7eae6a9477f923e..b3398798ec9f7eb8a11db29f262c071a1959082a 100644 (file)
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -2095,6 +2095,7 @@ to upconvert to 32b float internally?
        </reg32>
 
        <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
+               <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
                <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
                <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
        </reg32>
@@ -2201,6 +2202,7 @@ to upconvert to 32b float internally?
                <!-- per-mrt enable bit -->
                <bitfield name="ENABLE_BLEND" low="0" high="7"/>
                <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
+               <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
                <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
                <bitfield name="SAMPLE_MASK" low="16" high="31"/>
        </reg32>
@@ -2964,6 +2966,7 @@ to upconvert to 32b float internally?
        <reg32 offset="0xa989" name="SP_BLEND_CNTL">
                <bitfield name="ENABLED" pos="0" type="boolean"/>
                <bitfield name="UNK8" pos="8" type="boolean"/>
+               <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
                <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
        </reg32>
        <reg32 offset="0xa98a" name="SP_SRGB_CNTL">
@@ -2988,6 +2991,7 @@ to upconvert to 32b float internally?
                <bitfield name="RT7" low="28" high="31"/>
        </reg32>
        <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0">
+               <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
                <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
                <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
        </reg32>