ARM: Treat LDRD in ARM with an odd index as an undefined instruction.

diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index aa8bbf55ec1f0c8acff687ccfc400d51b866710f..59a6f126a808663ad91587612dc88c423b25a092 100644 (file)
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -122,8 +122,10 @@ def format AddrMode3() {{
           case 0x2:
             if (op1 & 0x1) {
                 %(ldrsb)s
-            } else {
+            } else if ((RT %% 2) == 0) {
                 %(ldrd)s
+            } else {
+                return new Unknown(machInst);
             }
           case 0x3:
             if (op1 & 0x1) {