intel/ir/gen12: Add SYNC hardware instruction.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/intel/compiler/brw_eu.cpp b/src/intel/compiler/brw_eu.cpp
index a8c3e55f65f0420daca548cb07fcb5a9ade8d645..54c8511ae8dcc0d738986052bd536d73c76b4183 100644 (file)
--- a/src/intel/compiler/brw_eu.cpp
+++ b/src/intel/compiler/brw_eu.cpp
@@ -467,6 +467,7 @@ enum gen {
 static const struct opcode_desc opcode_descs[] = {
    /* IR,                 HW,  name,      nsrc, ndst, gens */
    { BRW_OPCODE_ILLEGAL,  0,   "illegal", 0,    0,    GEN_ALL },
+   { BRW_OPCODE_SYNC,     1,   "sync",    1,    0,    GEN_GE(GEN12) },
    { BRW_OPCODE_MOV,      1,   "mov",     1,    1,    GEN_LT(GEN12) },
    { BRW_OPCODE_MOV,      97,  "mov",     1,    1,    GEN_GE(GEN12) },
    { BRW_OPCODE_SEL,      2,   "sel",     2,    1,    GEN_LT(GEN12) },

diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index 6250b50c691d2f467dc27ddea479501028182e99..7252e0cb4b15790145212c65fb1b9ede76aaaa50 100644 (file)
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -197,6 +197,7 @@ enum PACKED gen10_align1_3src_dst_horizontal_stride {
 enum opcode {
    /* These are the actual hardware instructions. */
    BRW_OPCODE_ILLEGAL,
+   BRW_OPCODE_SYNC,
    BRW_OPCODE_MOV,
    BRW_OPCODE_SEL,
    BRW_OPCODE_MOVI, /**< G45+ */

diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index 5c6b4dcd6a9134e50b69cd35ede30a9717eb314f..94976a12c000d5c658bbf57af6f9eeecb8e31161 100644 (file)
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -1042,6 +1042,7 @@ backend_instruction::has_side_effects() const
    case SHADER_OPCODE_SEND:
       return send_has_side_effects;
 
+   case BRW_OPCODE_SYNC:
    case VEC4_OPCODE_UNTYPED_ATOMIC:
    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: