fix wide luts

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index 62cb080d9cc530693eb7300c9a8336ab3fc7296a..93a49679c8bac3f9f6cace621fd7807142bb78d5 100644 (file)
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -104,27 +104,27 @@ module \$lut (A, Y);
     end else
     if (WIDTH == 5) begin
       wire f0, f1;
-      \$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[1:4]), .Y(f0));
-      \$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[1:4]), .Y(f1));
-      MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
+      \$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));
+      \$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));
+      MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));
     end else
     if (WIDTH == 6) begin
       wire f0, f1;
-      \$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[1:5]), .Y(f0));
-      \$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[1:5]), .Y(f1));
-      MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
+      \$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));
+      \$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));
+      MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));
     end else
     if (WIDTH == 7) begin
       wire f0, f1;
-      \$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[1:6]), .Y(f0));
-      \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[1:6]), .Y(f1));
-      MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
+      \$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
+      \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
+      MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));
     end else
     if (WIDTH == 8) begin
       wire f0, f1;
-      \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[1:7]), .Y(f0));
-      \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[1:7]), .Y(f1));
-      MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
+      \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
+      \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
+      MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));
     end else begin
       wire _TECHMAP_FAIL_ = 1;
     end

diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys
index f7e478c876ba9a98a263d63e12341e99f0691c49..4990be42166a66fb2c5a87ecc4b012947b310f04 100644 (file)
--- a/tests/arch/gowin/mux.ys
+++ b/tests/arch/gowin/mux.ys
@@ -15,33 +15,36 @@ select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 2 t:LUT4
+select -assert-count 4 t:LUT4
+select -assert-count 2 t:MUX2_LUT5
+select -assert-count 1 t:MUX2_LUT6
 select -assert-count 6 t:IBUF
 select -assert-count 1 t:OBUF
 
-select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
 
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 11 t:IBUF
 select -assert-count 1 t:OBUF
 
-select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
 
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
 select -assert-count 20 t:IBUF
 select -assert-count 1 t:OBUF
+show
 
-select -assert-none t:LUT4 t:LUT3 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D