targets: self.pll_sys --> pll_sys

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index fcb2a4f6e17e4cf7d40493ddf227a38132b36948..aeda2f901fba9bc2a4b85d3080ea49016f0b5c4e 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -31,7 +31,7 @@ class _CRG(Module):
 
         pll_locked = Signal()
         pll_fb = Signal()
-        self.pll_sys = Signal()
+        pll_sys = Signal()
         pll_sys4x = Signal()
         pll_sys4x_dqs = Signal()
         pll_clk200 = Signal()
@@ -47,7 +47,7 @@ class _CRG(Module):
 
                      # 100 MHz
                      p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0,
-                     o_CLKOUT0=self.pll_sys,
+                     o_CLKOUT0=pll_sys,
 
                      # 400 MHz
                      p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0,
@@ -65,7 +65,7 @@ class _CRG(Module):
                      p_CLKOUT4_DIVIDE=32, p_CLKOUT4_PHASE=0.0,
                      o_CLKOUT4=pll_clk50
             ),
-            Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
+            Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
             Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
             Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk),
             Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 460f0e47f570759b0eccdeb9450c0436f8188764..5702a5e23fb89fdb6efc6b29b73145a10c69994f 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -32,7 +32,7 @@ class _CRG(Module):
 
         pll_locked = Signal()
         pll_fb = Signal()
-        self.pll_sys = Signal()
+        pll_sys = Signal()
         pll_sys4x = Signal()
         pll_clk200 = Signal()
         self.specials += [
@@ -46,7 +46,7 @@ class _CRG(Module):
 
                      # 125MHz
                      p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0,
-                     o_CLKOUT0=self.pll_sys,
+                     o_CLKOUT0=pll_sys,
 
                      # 500MHz
                      p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0,
@@ -56,7 +56,7 @@ class _CRG(Module):
                      p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0,
                      o_CLKOUT2=pll_clk200
             ),
-            Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
+            Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
             Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
             Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
             AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~rst_n),

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 514c33e84d9991c011a9ec645bde048fe9da46fa..c2d2553d6b1009d6ea64080ea5463ebd5734615f 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -32,7 +32,7 @@ class _CRG(Module):
 
         pll_locked = Signal()
         pll_fb = Signal()
-        self.pll_sys = Signal()
+        pll_sys = Signal()
         pll_sys4x = Signal()
         pll_clk200 = Signal()
         self.specials += [
@@ -46,7 +46,7 @@ class _CRG(Module):
 
                      # 125MHz
                      p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0,
-                     o_CLKOUT0=self.pll_sys,
+                     o_CLKOUT0=pll_sys,
 
                      # 500MHz
                      p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0,
@@ -56,7 +56,7 @@ class _CRG(Module):
                      p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0,
                      o_CLKOUT2=pll_clk200
             ),
-            Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
+            Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
             Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
             Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
             AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst),

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index 1b6ff7164319a6c54c45158b94d7f58a875fc960..fb1e2e2d16059b6acd8c6c8df6ca7d134ee0fd98 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -28,7 +28,7 @@ class _CRG(Module):
 
         pll_locked = Signal()
         pll_fb = Signal()
-        self.pll_sys = Signal()
+        pll_sys = Signal()
         pll_sys2x = Signal()
         pll_sys2x_dqs = Signal()
         pll_clk200 = Signal()
@@ -43,7 +43,7 @@ class _CRG(Module):
 
                      # 100 MHz
                      p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0,
-                     o_CLKOUT0=self.pll_sys,
+                     o_CLKOUT0=pll_sys,
 
                      # 200 MHz
                      p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.0,
@@ -57,7 +57,7 @@ class _CRG(Module):
                      p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0,
                      o_CLKOUT3=pll_clk200
             ),
-            Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
+            Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
             Instance("BUFG", i_I=pll_sys2x, o_O=self.cd_sys2x.clk),
             Instance("BUFG", i_I=pll_sys2x_dqs, o_O=self.cd_sys2x_dqs.clk),
             Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 3a97e2aac5c6be92b83906ec914fd7cca18ff26c..1af07c7f8eb31e323f45a21d4ec439ee3528599c 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -31,7 +31,7 @@ class _CRG(Module):
 
         pll_locked = Signal()
         pll_fb = Signal()
-        self.pll_sys = Signal()
+        pll_sys = Signal()
         pll_sys4x = Signal()
         pll_sys4x_dqs = Signal()
         pll_clk200 = Signal()
@@ -46,7 +46,7 @@ class _CRG(Module):
 
                      # 100 MHz
                      p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0,
-                     o_CLKOUT0=self.pll_sys,
+                     o_CLKOUT0=pll_sys,
 
                      # 400 MHz
                      p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0,
@@ -60,7 +60,7 @@ class _CRG(Module):
                      p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0,
                      o_CLKOUT3=pll_clk200
             ),
-            Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
+            Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
             Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
             Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk),
             Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),