Fix simple_abc9/generate test with 1'bx at MSB

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index fc9da11732341260d5bac1a9e740a82ff5700345..d4887777924725c3c5a5c022b0d3193a62d36165 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -492,7 +492,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                        if (w->port_output) {
                                RTLIL::Wire *wire = module->wire(w->name);
                                log_assert(wire);
-                               for (int i = 0; i < GetSize(wire); i++)
+                               for (int i = 0; i < GetSize(w); i++)
                                        output_bits.insert({wire, i});
                        }
                }