bug 676: maxloc, use crternlogi to reduce op count

diff --git a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
index 1395d3fb2c39739259ef8f7727fc0f876cb107e3..f7b508b214662b1856528caab4ecb4fe961c8374 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
@@ -89,14 +89,14 @@ class DDFFirstTestCase(FHDLTestCase):
                 "mtcrf 128, 0",       # clear CR0 (in case VL=0?)
                 # while (i<n and a[i]>m):
                 "sv.minmax./ff=le/m=ge 4, *10, 4, 1", # uses r4 as accumulator
-                #"crternlogi 0,1,2,127"  # test greater/equal or VL=0
-                "cror 0,1,0",           # test for greater or equal, or VL=0
-                "cror 0,2,0",           # test for greater or equal, or VL=0
+                "crternlogi 0,1,2,127",  # test greater/equal or VL=0
+                #"cror 0,1,0",           # test for greater or equal, or VL=0
+                #"cror 0,2,0",           # test for greater or equal, or VL=0
                 "sv.creqv *19,*16,*16", # set mask on already-tested
                 "sv.crand *19,*19,0",   # clear if CR0=0
                 "sv.svstep/mr/m=so 1, 0, 6, 1",  # svstep: get vector dststep
                 "sv.creqv *16,*16,*16", # set mask on already-tested
-                "bc 12,0, -0x4c"            # CR0 lt bit clear, branch back
+                "bc 12,0, -0x48"            # CR0 lt bit clear, branch back
                         ])
         lst = list(lst)