build.plat: strip internal attributes from Verilog output.
authorwhitequark <cz@m-labs.hk>
Tue, 24 Sep 2019 14:54:22 +0000 (14:54 +0000)
committerwhitequark <cz@m-labs.hk>
Tue, 24 Sep 2019 14:56:00 +0000 (14:56 +0000)
Although useful for debugging, most external tools often complain
about such attributes (with notable exception of Vivado). As such,
it is better to emit Verilog with these attributes into a separate
file such as `design.debug.v` and only emit the attributes that were
explicitly placed by the user to `design.v`.

This still leaves the (*init*) attribute. See #220 for details.

nmigen/back/verilog.py
nmigen/build/plat.py
nmigen/vendor/lattice_ecp5.py
nmigen/vendor/lattice_ice40.py
nmigen/vendor/xilinx_7series.py
nmigen/vendor/xilinx_spartan_3_6.py

index a70a35b29dd68fea9ba5ac07d9746e4221df69d0..118d0adf2f09db0294b86cb5c385041d7440d196 100644 (file)
@@ -21,14 +21,18 @@ def _yosys_version():
     return tuple(map(int, tag.split("."))), offset
 
 
-def _convert_il_text(il_text, strip_src):
+def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False):
     version, offset = _yosys_version()
     if version < (0, 9):
         raise YosysError("Yosys %d.%d is not suppored", *version)
 
     attr_map = []
-    if strip_src:
+    if strip_internal_attrs:
+        attr_map.append("-remove generator")
+        attr_map.append("-remove top")
         attr_map.append("-remove src")
+        attr_map.append("-remove nmigen.hierarchy")
+        attr_map.append("-remove nmigen.decoding")
 
     script = """
 # Convert nMigen's RTLIL to readable Verilog.
@@ -41,10 +45,13 @@ proc_arst
 proc_dff
 proc_clean
 memory_collect
-attrmap {}
+attrmap {attr_map}
+attrmap -modattr {attr_map}
 write_verilog -norename
-""".format(il_text, " ".join(attr_map),
-           prune="# " if version == (0, 9) and offset == 0 else "")
+""".format(rtlil_text,
+        prune="# " if version == (0, 9) and offset == 0 else "",
+        attr_map=" ".join(attr_map),
+    )
 
     popen = subprocess.Popen([require_tool("yosys"), "-q", "-"],
         stdin=subprocess.PIPE,
@@ -58,11 +65,11 @@ write_verilog -norename
         return verilog_text
 
 
-def convert_fragment(*args, strip_src=False, **kwargs):
-    il_text, name_map = rtlil.convert_fragment(*args, **kwargs)
-    return _convert_il_text(il_text, strip_src), name_map
+def convert_fragment(*args, strip_internal_attrs=False, **kwargs):
+    rtlil_text, name_map = rtlil.convert_fragment(*args, **kwargs)
+    return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs), name_map
 
 
-def convert(*args, strip_src=False, **kwargs):
-    il_text = rtlil.convert(*args, **kwargs)
-    return _convert_il_text(il_text, strip_src)
+def convert(*args, strip_internal_attrs=False, **kwargs):
+    rtlil_text = rtlil.convert(*args, **kwargs)
+    return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs)
index 30800ec2e29614f3f87145c8296520cd3c5f9b99..0a2d28e0c6010cf1347867f84bf2d0c00e1e8da1 100644 (file)
@@ -272,12 +272,16 @@ class TemplatedPlatform(Platform):
         # and to incorporate the nMigen version into generated code.
         autogenerated = "Automatically generated by nMigen {}. Do not edit.".format(__version__)
 
-        name_map = None
-        def emit_design(backend):
-            nonlocal name_map
-            backend_mod = {"rtlil": rtlil, "verilog": verilog}[backend]
-            design_text, name_map = backend_mod.convert_fragment(fragment, name=name)
-            return design_text
+        rtlil_text, name_map = rtlil.convert_fragment(fragment, name=name)
+
+        def emit_rtlil():
+            return rtlil_text
+
+        def emit_verilog():
+            return verilog._convert_rtlil_text(rtlil_text, strip_internal_attrs=True)
+
+        def emit_debug_verilog():
+            return verilog._convert_rtlil_text(rtlil_text, strip_internal_attrs=False)
 
         def emit_commands(format):
             commands = []
@@ -341,7 +345,9 @@ class TemplatedPlatform(Platform):
             return compiled.render({
                 "name": name,
                 "platform": self,
-                "emit_design": emit_design,
+                "emit_rtlil": emit_rtlil,
+                "emit_verilog": emit_verilog,
+                "emit_debug_verilog": emit_debug_verilog,
                 "emit_commands": emit_commands,
                 "get_tool": get_tool,
                 "get_override": get_override,
index e46f30fa48793e3dbf383c74f37ce9b7684a31cc..8852fb82eab61d8a69f6440ef9e352c5375496fe 100644 (file)
@@ -101,7 +101,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         **TemplatedPlatform.build_script_templates,
         "{{name}}.il": r"""
             # {{autogenerated}}
-            {{emit_design("rtlil")}}
+            {{emit_rtlil()}}
         """,
         "{{name}}.ys": r"""
             # {{autogenerated}}
@@ -182,7 +182,11 @@ class LatticeECP5Platform(TemplatedPlatform):
         """,
         "{{name}}.v": r"""
             /* {{autogenerated}} */
-            {{emit_design("verilog")}}
+            {{emit_verilog()}}
+        """,
+        "{{name}}.debug.v": r"""
+            /* {{autogenerated}} */
+            {{emit_debug_verilog()}}
         """,
         "{{name}}.tcl": r"""
             prj_project new -name {{name}} -impl impl -impl_dir top_impl \
index ffbbd0c99792aedd9eb1021799c79c50389e42c4..cdd488f0c9b494c304b39854bdf0d099c2062718 100644 (file)
@@ -105,7 +105,7 @@ class LatticeICE40Platform(TemplatedPlatform):
         **TemplatedPlatform.build_script_templates,
         "{{name}}.il": r"""
             # {{autogenerated}}
-            {{emit_design("rtlil")}}
+            {{emit_rtlil()}}
         """,
         "{{name}}.ys": r"""
             # {{autogenerated}}
@@ -196,7 +196,11 @@ class LatticeICE40Platform(TemplatedPlatform):
         """,
         "{{name}}.v": r"""
             /* {{autogenerated}} */
-            {{emit_design("verilog")}}
+            {{emit_verilog()}}
+        """,
+        "{{name}}.debug.v": r"""
+            /* {{autogenerated}} */
+            {{emit_debug_verilog()}}
         """,
         "{{name}}_lse.prj": r"""
             # {{autogenerated}}
index ca42054512af1ea585b1c9e76ebc40de32defce4..0ff197247a1c2cb5d4b17b1a7b69d64031f9180f 100644 (file)
@@ -63,7 +63,11 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         """,
         "{{name}}.v": r"""
             /* {{autogenerated}} */
-            {{emit_design("verilog")}}
+            {{emit_verilog()}}
+        """,
+        "{{name}}.debug.v": r"""
+            /* {{autogenerated}} */
+            {{emit_debug_verilog()}}
         """,
         "{{name}}.tcl": r"""
             # {{autogenerated}}
index 57ba13af7b78585ac893de9ce2ded2ab85293611..6945542c5f27f87b8823a862eb43cf024a13e28e 100644 (file)
@@ -93,7 +93,11 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
         """,
         "{{name}}.v": r"""
             /* {{autogenerated}} */
-            {{emit_design("verilog")}}
+            {{emit_verilog()}}
+        """,
+        "{{name}}.debug.v": r"""
+            /* {{autogenerated}} */
+            {{emit_debug_verilog()}}
         """,
         "{{name}}.prj": r"""
             # {{autogenerated}}