projects
/
riscv-isa-sim.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
d539f3f
)
clarify sv cam table
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 25 Sep 2018 01:17:49 +0000
(
02:17
+0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 25 Sep 2018 01:17:49 +0000
(
02:17
+0100)
riscv/sv.h
patch
|
blob
|
history
diff --git
a/riscv/sv.h
b/riscv/sv.h
index ba4092646da3d26fa0fa815243fe9167a9b0e863..58e5724863a1c92b8afa7e16d2a0eeff9385a808 100644
(file)
--- a/
riscv/sv.h
+++ b/
riscv/sv.h
@@
-5,6
+5,8
@@
// this table is for the CSRs (4? for RV32E, 16 for other types)
// it's a CAM that's used to generate 2 tables (below)
+// just as in RV, writing to entries in this CAM *clears*
+// all entries with a higher index
typedef struct {
unsigned int type : 1; // 0=INT, 1=FP
unsigned int regkey : 5; // 5 bits