(no commit message)

diff --git a/nlnet_2023_svp64_riscv.mdwn b/nlnet_2023_svp64_riscv.mdwn
index 7a60e21c9b82c21b49fe323827076a8a05b3d0bc..45838dd8c1ffdd23ef6e71aa392a2a85023b3565 100644 (file)
--- a/nlnet_2023_svp64_riscv.mdwn
+++ b/nlnet_2023_svp64_riscv.mdwn
@@ -62,7 +62,7 @@ Key phases of this project are:
 
 * Implementation of Simple-V in the Libre-SOC Simulator, ISACaller.
 
-* Assembler and disassembler of RISC-V instructions and also SVP64 in the Libre-SOC infrastructure.
+* Definition of assembler and disassembler for RISC-V instructions and also SVP64 in the Libre-SOC infrastructure.
 
 * Upgrading (with the newly created instructions and forms) sv-spike assembler development which was prototyped previously for Simple-V Specification:
   <https://git.libre-soc.org/?p=riscv-isa-sim.git;a=shortlog;h=refs/heads/sv>