gen/sim, fhdl: remove port.we_granularity limitation on simulations

We have to find a way to eliminate all replaced memory ports from specials,
here we use a workaround and remove remaining _MemPorts before simulating.

If possible, proper way would be to remove replaced ports from specials.
Another solution can to remove all ports that are no longer associated with
a Memory.

diff --git a/litex/gen/fhdl/simplify.py b/litex/gen/fhdl/simplify.py
index c85b19c297514ea11c4f14f4cac0a8f3482d1cc4..5f31a470b7d8282897713b6813dcdd067c9adc58 100644 (file)
--- a/litex/gen/fhdl/simplify.py
+++ b/litex/gen/fhdl/simplify.py
@@ -6,15 +6,17 @@ from litex.gen.util.misc import gcd_multiple
 
 class FullMemoryWE(ModuleTransformer):
     def __init__(self):
-        self.replacments = dict()
+        self.replacements = dict()
 
     def transform_fragment(self, i, f):
         newspecials = set()
+        replaced_ports = set()
 
         for orig in f.specials:
             if not isinstance(orig, Memory):
                 newspecials.add(orig)
                 continue
+
             global_granularity = gcd_multiple([p.we_granularity if p.we_granularity else orig.width for p in orig.ports])
             if global_granularity == orig.width:
                 newspecials.add(orig)  # nothing to do
@@ -44,8 +46,12 @@ class FullMemoryWE(ModuleTransformer):
                             clock_domain=port.clock.cd)
                         newmem.ports.append(newport)
                         newspecials.add(newport)
-                self.replacments[orig] = newmems
 
+                for port in orig.ports:
+                    replaced_ports.add(port)
+                self.replacements[orig] = newmems
+
+        newspecials -= replaced_ports
         f.specials = newspecials
 
 
@@ -75,8 +81,6 @@ class MemoryToArray(ModuleTransformer):
                 storage.append(mem_storage)
 
             for port in mem.ports:
-                if port.we_granularity:
-                    raise NotImplementedError
                 try:
                     sync = f.sync[port.clock.cd]
                 except KeyError:

diff --git a/litex/gen/sim/core.py b/litex/gen/sim/core.py
index 928e9a32bddb7b74a7169d2c95378a0eaed0c09a..d9b7adf2c3dea4b619cfead5fbaedb524612d8be 100644 (file)
--- a/litex/gen/sim/core.py
+++ b/litex/gen/sim/core.py
@@ -11,7 +11,7 @@ from litex.gen.fhdl.bitcontainer import value_bits_sign
 from litex.gen.fhdl.tools import (list_targets, list_signals,
                               insert_resets, lower_specials)
 from litex.gen.fhdl.simplify import MemoryToArray
-from litex.gen.fhdl.specials import _MemoryLocation
+from litex.gen.fhdl.specials import _MemoryLocation, _MemoryPort
 from litex.gen.sim.vcd import VCDWriter, DummyVCDWriter
 
 
@@ -230,6 +230,13 @@ class Simulator:
         fs, lowered = lower_specials(overrides={}, specials=self.fragment.specials)
         self.fragment += fs
         self.fragment.specials -= lowered
+        # FIXME: Remaining replaced ports workaround
+        remaining_memory_ports = set()
+        for s in self.fragment.specials:
+            if isinstance(s, _MemoryPort):
+                remaining_memory_ports.add(s)
+        self.fragment.specials -= remaining_memory_ports
+        # FIXME: Remaining replaced ports workaround
         if self.fragment.specials:
             raise ValueError("Could not lower all specials", self.fragment.specials)