* gcc.target/aarch64/pragma_cpp_predefs_1.c: New test.
* gcc.target/aarch64/target_attr_1.c: Likewise.
* gcc.target/aarch64/target_attr_2.c: Likewise.
* gcc.target/aarch64/target_attr_3.c: Likewise.
* gcc.target/aarch64/target_attr_4.c: Likewise.
* gcc.target/aarch64/target_attr_5.c: Likewise.
* gcc.target/aarch64/target_attr_6.c: Likewise.
* gcc.target/aarch64/target_attr_7.c: Likewise.
* gcc.target/aarch64/target_attr_8.c: Likewise.
* gcc.target/aarch64/target_attr_9.c: Likewise.
* gcc.target/aarch64/target_attr_10.c: Likewise.
* gcc.target/aarch64/target_attr_11.c: Likewise.
* gcc.target/aarch64/target_attr_12.c: Likewise.
* gcc.target/aarch64/target_attr_13.c: Likewise.
* gcc.target/aarch64/target_attr_14.c: Likewise.
* gcc.target/aarch64/target_attr_15.c: Likewise.
From-SVN: r226565
+2015-08-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * gcc.target/aarch64/pragma_cpp_predefs_1.c: New test.
+ * gcc.target/aarch64/target_attr_1.c: Likewise.
+ * gcc.target/aarch64/target_attr_2.c: Likewise.
+ * gcc.target/aarch64/target_attr_3.c: Likewise.
+ * gcc.target/aarch64/target_attr_4.c: Likewise.
+ * gcc.target/aarch64/target_attr_5.c: Likewise.
+ * gcc.target/aarch64/target_attr_6.c: Likewise.
+ * gcc.target/aarch64/target_attr_7.c: Likewise.
+ * gcc.target/aarch64/target_attr_8.c: Likewise.
+ * gcc.target/aarch64/target_attr_9.c: Likewise.
+ * gcc.target/aarch64/target_attr_10.c: Likewise.
+ * gcc.target/aarch64/target_attr_11.c: Likewise.
+ * gcc.target/aarch64/target_attr_12.c: Likewise.
+ * gcc.target/aarch64/target_attr_13.c: Likewise.
+ * gcc.target/aarch64/target_attr_14.c: Likewise.
+ * gcc.target/aarch64/target_attr_15.c: Likewise.
+
2015-08-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/aarch64/target_attr_crypto_ice_1.c: New test.
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8-a+crypto" } */
+
+/* Test that pragma option pushing and popping works.
+ Also that CPP predefines redefinitions on #pragma works. */
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8-a+nofp+nosimd")
+#ifdef __ARM_FEATURE_FMA
+#error "__ARM_FEATURE_FMA is defined but should not be!"
+#endif
+
+#ifdef __ARM_FP
+#error "__ARM_FP is defined but should not be!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8-a+fp+nosimd")
+#ifndef __ARM_FP
+#error "__ARM_FP is not defined but should be!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON is defined but should not be!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8-a+fp+simd")
+
+#ifndef __ARM_NEON
+#error "__ARM_NEON is not defined but should be!"
+#endif
+
+#ifdef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO is defined but should not be!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8-a+fp+simd+crypto")
+
+#ifndef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO is not defined but should be!"
+#endif
+
+#pragma GCC pop_options
+
+#ifndef __ARM_NEON
+#error "__ARM_NEON is not defined but should be!"
+#endif
+
+#ifdef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO is defined but should not be!"
+#endif
+
+
+#pragma GCC pop_options
+
+#ifndef __ARM_FP
+#error "__ARM_FP is not defined but should be!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON is defined but should not be!"
+#endif
+
+#pragma GCC pop_options
+
+#ifdef __ARM_FP
+#error "__ARM_FP is defined but should not be!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON is defined but should not be!"
+#endif
+
+/* And again, but using cpu=. */
+
+#pragma GCC push_options
+#pragma GCC target ("cpu=cortex-a53+nofp+nosimd")
+#ifdef __ARM_FEATURE_FMA
+#error "__ARM_FEATURE_FMA is defined but should not be!"
+#endif
+
+#ifdef __ARM_FP
+#error "__ARM_FP is defined but should not be!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("cpu=cortex-a53+fp+nosimd")
+#ifndef __ARM_FP
+#error "__ARM_FP is not defined but should be!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON is defined but should not be!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("cpu=cortex-a53+fp+simd+nocrypto")
+
+#ifndef __ARM_NEON
+#error "__ARM_NEON is not defined but should be!"
+#endif
+
+#ifdef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO is defined but should not be!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("cpu=cortex-a53+fp+simd+crypto")
+
+#ifndef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO is not defined but should be!"
+#endif
+
+
+#pragma GCC pop_options
+
+#ifndef __ARM_NEON
+#error "__ARM_NEON is not defined but should be!"
+#endif
+
+#ifdef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO is defined but should not be!"
+#endif
+
+
+#pragma GCC pop_options
+
+#ifndef __ARM_FP
+#error "__ARM_FP is not defined but should be!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON is defined but should not be!"
+#endif
+
+#pragma GCC pop_options
+
+#ifdef __ARM_FP
+#error "__ARM_FP is defined but should not be!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON is defined but should not be!"
+#endif
+
+/* And again, but using just the ISA extensions. */
+
+#pragma GCC push_options
+#pragma GCC target ("+nofp")
+#ifdef __ARM_FEATURE_FMA
+#error "__ARM_FEATURE_FMA is defined but should not be!"
+#endif
+
+#ifdef __ARM_FP
+#error "__ARM_FP is defined but should not be!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("+fp+nosimd")
+#ifndef __ARM_FP
+#error "__ARM_FP is not defined but should be!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON is defined but should not be!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("+fp+simd+nocrypto")
+
+#ifndef __ARM_NEON
+#error "__ARM_NEON is not defined but should be!"
+#endif
+
+#ifdef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO is defined but should not be!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("+fp+simd+crypto")
+
+#ifndef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO is not defined but should be!"
+#endif
+
+#pragma GCC pop_options
+
+#ifndef __ARM_NEON
+#error "__ARM_NEON is not defined but should be!"
+#endif
+
+#ifdef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO is defined but should not be!"
+#endif
+
+
+#pragma GCC pop_options
+
+#ifndef __ARM_FP
+#error "__ARM_FP is not defined but should be!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON is defined but should not be!"
+#endif
+
+#pragma GCC pop_options
+
+#ifdef __ARM_FP
+#error "__ARM_FP is defined but should not be!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON is defined but should not be!"
+#endif
+
+/* Make sure that general-regs-only works too. */
+#pragma GCC push_options
+#pragma GCC target ("general-regs-only")
+#ifdef __ARM_FEATURE_FMA
+#error "__ARM_FEATURE_FMA is defined but should not be!"
+#endif
+
+#ifdef __ARM_FP
+#error "__ARM_FP is defined but should not be!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON is defined but should not be!"
+#endif
+
+#ifdef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO is defined but should not be!"
+#endif
+
+#pragma GCC pop_options
+
+/* Also check that crc re-defines work. */
+#pragma GCC target ("+nocrc")
+#ifdef __ARM_FEATURE_CRC32
+#error "__ARM_FEATURE_CRC32 is defined but should not be!"
+#endif
+
+#pragma GCC target ("+crc")
+#ifndef __ARM_FEATURE_CRC32
+#error "__ARM_FEATURE_CRC32 is not defined but should be!"
+#endif
+
+int
+foo (int a)
+{
+ return a;
+}
--- /dev/null
+/* { dg-do assemble } */
+/* { dg-options "-O2 -mcpu=thunderx -save-temps" } */
+
+/* Test that cpu attribute overrides the command-line -mcpu. */
+
+__attribute__ ((target ("cpu=cortex-a72.cortex-a53")))
+int
+foo (int a)
+{
+ return a + 1;
+}
+
+/* { dg-final { scan-assembler "//.tune cortex-a72.cortex-a53" } } */
+/* { dg-final { scan-assembler-not "thunderx" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8-a+simd" } */
+
+/* Using a SIMD intrinsic from a function tagged with nosimd should fail
+ due to inlining rules. */
+
+#include "arm_neon.h"
+
+__attribute__ ((target ("+nosimd")))
+uint8x16_t
+foo (uint8x16_t a, uint8x16_t b, uint8x16_t c)
+{
+ return vbslq_u8 (a, b, c); /* { dg-error "called from here" } */
+}
+
+/* { dg-error "inlining failed in call to always_inline" "" { target *-*-* } 0 } */
--- /dev/null
+/* { dg-do compile } */
+
+/* Reject the negated form of non-negatable attributes. */
+
+__attribute__ ((target ("no-general-regs-only")))
+int
+foo (int a)
+{
+ return a + 1;
+}
+
+/* { dg-error "does not allow a negated form" "" { target *-*-* } 0 } */
+/* { dg-error "is invalid" "" { target *-*-* } 0 } */
--- /dev/null
+/* { dg-do compile } */
+
+/* Reject arguments to attributes that do not accept any. */
+
+__attribute__ ((target ("general-regs-only=+crc")))
+int
+foo (int a)
+{
+ return a + 1;
+}
+
+/* { dg-error "does not accept an argument" "" { target *-*-* } 0 } */
+/* { dg-error "is invalid" "" { target *-*-* } 0 } */
--- /dev/null
+/* { dg-do assemble } */
+/* { dg-options "-O2 -march=armv8-a+crc+crypto" } */
+
+#include "arm_acle.h"
+
+/* Make sure that 'crypto' is not required to compile an intrinsic
+ from arm_acle.h in a non-crypto function. Tests that arm_acle.h
+ properly clears the architectural features in its initial target
+ pragma. */
+
+__attribute__ ((target ("+crc+nocrypto")))
+int
+foo (uint32_t a, uint8_t b)
+{
+ return __crc32b (a, b);
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -save-temps" } */
+
+/* Inlining non-strict-align functions into strict-align
+ functions is allowed. */
+
+int
+bar (int a)
+{
+ return a - 6;
+}
+
+__attribute__ ((target ("strict-align")))
+int
+bam (int a)
+{
+ return a - bar (a);
+}
+
+/* { dg-final { scan-assembler-not "bl.*bar" } } */
--- /dev/null
+/* { dg-do assemble } */
+/* { dg-options "-march=armv8-a+crypto -save-temps" } */
+
+/* Check that "+nothing" clears the ISA flags. */
+
+__attribute__ ((target ("+nothing")))
+int
+foo (int a)
+{
+ return a + 1;
+}
+
+/* { dg-final { scan-assembler-not "\\+fp" } } */
+/* { dg-final { scan-assembler-not "\\+crypto" } } */
+/* { dg-final { scan-assembler-not "\\+simd" } } */
--- /dev/null
+/* { dg-do assemble } */
+/* { dg-options "-O2 -mcpu=cortex-a57 -ftree-vectorize -fdump-tree-vect-all" } */
+
+/* The various ways to turn off simd availability should
+ turn off vectorization. */
+
+__attribute__ ((target ("+nosimd")))
+int
+baz (int *a)
+{
+ for (int i = 0; i < 1024; i++)
+ a[i] += 5;
+}
+
+__attribute__ ((target ("arch=armv8-a+nosimd")))
+int
+baz2 (int *a)
+{
+ for (int i = 0; i < 1024; i++)
+ a[i] += 5;
+}
+
+__attribute__ ((target ("cpu=cortex-a53+nosimd")))
+int
+baz3 (int *a)
+{
+ for (int i = 0; i < 1024; i++)
+ a[i] += 5;
+}
+
+__attribute__ ((target ("general-regs-only")))
+int
+baz4 (int *a)
+{
+ for (int i = 0; i < 1024; i++)
+ a[i] += 5;
+}
+
+/* { dg-final { scan-tree-dump-not "vectorized 1 loops" "vect" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -mno-fix-cortex-a53-835769 -save-temps" } */
+
+/* Check that the attribute overrides the command line option
+ and the fix is applied once. */
+
+__attribute__ ((target ("fix-cortex-a53-835769")))
+unsigned long
+test (unsigned long a, double b, unsigned long c,
+ unsigned long d, unsigned long *e)
+{
+ double result;
+ volatile unsigned long tmp = *e;
+ __asm__ __volatile ("// %0, %1"
+ : "=w" (result)
+ : "0" (b)
+ : /* No clobbers. */);
+ return c * d + d;
+}
+
+unsigned long
+test2 (unsigned long a, double b, unsigned long c,
+ unsigned long d, unsigned long *e)
+{
+ double result;
+ volatile unsigned long tmp = *e;
+ __asm__ __volatile ("// %0, %1"
+ : "=w" (result)
+ : "0" (b)
+ : /* No clobbers. */);
+ return c * d + d;
+}
+
+/* { dg-final { scan-assembler-times "between mem op and" 1 } } */
--- /dev/null
+/* { dg-do assemble } */
+/* { dg-options "-O2 -march=armv8-a+nocrc -save-temps" } */
+
+#include "arm_acle.h"
+
+/* Check that enabling an ISA feature using an attribute in a file
+ compiled without that attribute works. */
+
+__attribute__ ((target ("+crc")))
+uint32_t
+foo (uint32_t a, uint8_t b)
+{
+ return __crc32b (a, b);
+}
+
+__attribute__ ((target ("arch=armv8-a+crc")))
+uint32_t
+fooarch (uint32_t a, uint8_t b)
+{
+ return __crc32b (a, b);
+}
+
+__attribute__ ((target ("cpu=cortex-a53+crc")))
+uint32_t
+foocpu (uint32_t a, uint8_t b)
+{
+ return __crc32b (a, b);
+}
+
+/* { dg-final { scan-assembler-times "crc32b\tw..?, w..?, w..?\n" 3 } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -save-temps" } */
+
+/* Make sure that bar is inlined into bam. */
+
+__attribute__ ((target ("arch=armv8-a+nocrc")))
+int
+bar (int a)
+{
+ return a - 6;
+}
+
+__attribute__ ((target ("cpu=cortex-a53+nocrc")))
+int
+bam (int a)
+{
+ return a - bar (a);
+}
+
+/* { dg-final { scan-assembler-not "bl.*bar" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -save-temps" } */
+
+/* Inlining strict-align functions into non-strict align
+ functions is not allowed. */
+
+__attribute__ ((target ("strict-align")))
+int
+bar (int a)
+{
+ return a - 6;
+}
+
+int
+bam (int a)
+{
+ return a - bar (a);
+}
+
+/* { dg-final { scan-assembler "bl.*bar" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=thunderx -save-temps" } */
+
+/* Make sure that #pragma overrides command line option and
+ target attribute overrides the pragma. */
+
+#pragma GCC target ("cpu=xgene1")
+
+int
+bar (int a)
+{
+ return a - 6;
+}
+
+__attribute__ ((target ("tune=cortex-a53")))
+int
+bam (int a)
+{
+ return a - bar (a);
+}
+
+/* { dg-final { scan-assembler-times "//.tune xgene1" 1 } } */
+/* { dg-final { scan-assembler-times "//.tune cortex-a53" 1 } } */
+/* { dg-final { scan-assembler-not "thunderx" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -save-temps" } */
+
+/* bar has a subset set of the architectural flags of bam.
+ Inlining should be allowed. */
+
+__attribute__ ((target ("arch=armv8-a+nocrc")))
+int
+bar (int a)
+{
+ return a - 6;
+}
+
+__attribute__ ((target ("arch=armv8-a+crc")))
+int
+bam (int a)
+{
+ return a - bar (a);
+}
+
+
+/* { dg-final { scan-assembler-not "bl.*bar" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -save-temps" } */
+
+/* bar does not have a subset of architectural flags of bam.
+ Inlining should be rejected. */
+
+__attribute__ ((target ("arch=armv8-a+crc")))
+int
+bar (int a)
+{
+ return a - 6;
+}
+
+__attribute__ ((target ("arch=armv8-a+nocrc")))
+int
+bam (int a)
+{
+ return a - bar (a);
+}
+
+
+/* { dg-final { scan-assembler "bl.*bar" } } */
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