for (auto module_it : design->modules)
{
RTLIL::Module *module = module_it.second;
- if ((module->get_bool_attribute("\\placeholder")) > 0)
+ if (module->get_bool_attribute("\\placeholder"))
continue;
if (module->processes.size() != 0)
if (!design->selected_module(module->name))
continue;
if (design->selected_whole_module(module->name)) {
- if (module->get_bool_attribute("\\placeholder") > 0) {
+ if (module->get_bool_attribute("\\placeholder")) {
log("Skipping placeholder module %s.\n", id2cstr(module->name));
continue;
} else
if (format != "ps") {
int modcount = 0;
for (auto &mod_it : design->modules) {
- if (mod_it.second->get_bool_attribute("\\placeholder") > 0)
+ if (mod_it.second->get_bool_attribute("\\placeholder"))
continue;
if (mod_it.second->cells.empty() && mod_it.second->connections.empty())
continue;
logmap_all();
for (auto &it : design->modules)
- if (design->selected(it.second))
+ if (design->selected(it.second) && !it.second->get_bool_attribute("\\placeholder"))
dfflibmap(design, it.second);
cell_mappings.clear();