cores/up5ksram: optimize bus.adr decoding

diff --git a/litex/soc/cores/up5kspram.py b/litex/soc/cores/up5kspram.py
index 4a790d1895ded2f202574c9aac07e010e1351d69..80580169166a31cbbcf6b1c3ac7ab60c7652f9b5 100644 (file)
--- a/litex/soc/cores/up5kspram.py
+++ b/litex/soc/cores/up5kspram.py
@@ -47,7 +47,7 @@ class Up5kSPRAM(Module):
                 wren = Signal()
                 self.comb += [
                     datain.eq(self.bus.dat_w[16*w:16*(w+1)]),
-                    If(self.bus.adr[14:16] == d,
+                    If(self.bus.adr[14:14+log2_int(depth_cascading)+1] == d,
                         wren.eq(self.bus.we & self.bus.stb & self.bus.cyc),
                         self.bus.dat_r[16*w:16*(w+1)].eq(dataout)
                     ),