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fix format in debug log
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 8 Oct 2022 23:35:34 +0000 (00:35 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 8 Oct 2022 23:35:34 +0000 (00:35 +0100)
src/openpower/decoder/isa/caller.py patch | blob | history

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 35858b9d657db1eee799c45116423382afa063af..ee3453631075526a81b10a6927854f749f844bed 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -2201,7 +2201,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
             reg_prefix = 'r'
         # check zeroing due to predicate bit being zero
         if self.is_svp64_mode and self.pred_dst_zero:
-            log('zeroing reg %d %s' % (regnum, str(output)), is_vec)
+            log('zeroing reg %s %s' % (str(regnum), str(output)), is_vec)
             output = SelectableInt(0, 256)
         log("write reg %s%s 0x%x ew %d" % (reg_prefix, str(regnum),
                                            output.value, ew_dst),