Signed-off-by: Clifford Wolf <clifford@clifford.at>
/wolf_goat_cabbage
+/primegen
--- /dev/null
+[options]
+mode cover
+depth 1
+
+[engines]
+smtbmc --dumpsmt2 --stbv z3
+
+[script]
+read_verilog -formal primegen.v
+prep -top primegen
+
+[files]
+primegen.v
--- /dev/null
+module primegen;
+ wire [31:0] prime = $anyconst;
+ wire [15:0] factor = $allconst;
+
+ always @* begin
+ if (1 < factor && factor < prime)
+ assume((prime % factor) != 0);
+ assume(prime > 1000000000);
+ cover(1);
+ end
+endmodule