fixedsync/minor_31: add lqarx because I'm adding the others anyway

diff --git a/openpower/isa/fixedsync.mdwn b/openpower/isa/fixedsync.mdwn
index 583ef20e73f1a3142c51712756bb636a2209f63c..5a5998f6ac2accc461d18e114a96a6f8040f2499 100644 (file)
--- a/openpower/isa/fixedsync.mdwn
+++ b/openpower/isa/fixedsync.mdwn
@@ -89,6 +89,24 @@ Special Registers Altered:
 
     None
 
+# Load Quadword And Reserve Indexed
+
+X-Form
+
+* lqarx RTp,RA,RB,EH
+
+Pseudo-code:
+
+    EA <- (RA|0) + (RB)
+    RESERVE <- 1
+    RESERVE_LENGTH <- 16
+    RESERVE_ADDR <- real_addr(EA)
+    RTp <- MEM(EA, 16)
+
+Special Registers Altered:
+
+    None
+
 # Store Byte Conditional Indexed
 
 X-Form

diff --git a/openpower/isatables/LDSTRM-2P-2S1D.csv b/openpower/isatables/LDSTRM-2P-2S1D.csv
index e554c4333ff8225f4849b110a75e3591b2c9a3c4..072238dab682e3b51b59ac8f92356f791e295b41 100644 (file)
--- a/openpower/isatables/LDSTRM-2P-2S1D.csv
+++ b/openpower/isatables/LDSTRM-2P-2S1D.csv
@@ -6,6 +6,7 @@ lbarx,LDST_IDX,,2P,EXTRA2,EN,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
 ldarx,LDST_IDX,,2P,EXTRA2,EN,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
 lbzx,LDST_IDX,,2P,EXTRA2,EN,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
 lharx,LDST_IDX,,2P,EXTRA2,EN,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+lqarx,LDST_IDX,,2P,EXTRA2,EN,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
 lhzx,LDST_IDX,,2P,EXTRA2,EN,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
 lwax,LDST_IDX,,2P,EXTRA2,EN,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
 lhax,LDST_IDX,,2P,EXTRA2,EN,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0

diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
index f6a9c6bbd71466d4d5663bef4c1e9c8c1b697975..07544f21b9e6e2e8e18844d2163e114e7bd3bc89 100644 (file)
--- a/openpower/isatables/minor_31.csv
+++ b/openpower/isatables/minor_31.csv
@@ -118,6 +118,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b1100110101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,cix,0,0,0,NONE,0,0,lhzcix,X,,,
 0b0100110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzux,X,,,
 0b0100010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhzx,X,,,
+0b0100010100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,1,0,0,NONE,0,1,lqarx,X,,,FIXME: should probably be is16B and RTp
 0b0000010100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,1,0,0,NONE,0,1,lwarx,X,,,
 0b0101110101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,1,1,0,0,0,NONE,0,1,lwaux,X,,,
 0b0101010101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,1,0,0,0,0,NONE,0,1,lwax,X,,,