ARM: Keep the warnings to a minimum.

These warnings still need to be addresses, but pages of them is
counterproductive.

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 0ba62f08ddfe2433e95a34df9c18181bf23fc0ee..20cddcff16c5b808a20bfd3fdab466fc51e92e57 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -180,10 +180,10 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
     }
     switch (misc_reg) {
       case MISCREG_CLIDR:
-        warn("The clidr register always reports 0 caches.\n");
+        warn_once("The clidr register always reports 0 caches.\n");
         break;
       case MISCREG_CCSIDR:
-        warn("The ccsidr register isn't implemented and "
+        warn_once("The ccsidr register isn't implemented and "
                 "always reads as 0.\n");
         break;
       case MISCREG_ID_PFR0:
@@ -268,7 +268,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
             }
             break;
           case MISCREG_CSSELR:
-            warn("The csselr register isn't implemented.\n");
+            warn_once("The csselr register isn't implemented.\n");
             break;
           case MISCREG_FPSCR:
             {
@@ -319,7 +319,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
             return;
           case MISCREG_TLBIALLIS:
           case MISCREG_TLBIALL:
-            warn("Need to flush all TLBs in MP\n");
+            warn_once("Need to flush all TLBs in MP\n");
             tc->getITBPtr()->flushAll();
             tc->getDTBPtr()->flushAll();
             return;
@@ -331,7 +331,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
             return;
           case MISCREG_TLBIMVAIS:
           case MISCREG_TLBIMVA:
-            warn("Need to flush all TLBs in MP\n");
+            warn_once("Need to flush all TLBs in MP\n");
             tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
                     bits(newVal, 7,0));
             tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
@@ -339,13 +339,13 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
             return;
           case MISCREG_TLBIASIDIS:
           case MISCREG_TLBIASID:
-            warn("Need to flush all TLBs in MP\n");
+            warn_once("Need to flush all TLBs in MP\n");
             tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
             tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
             return;
           case MISCREG_TLBIMVAAIS:
           case MISCREG_TLBIMVAA:
-            warn("Need to flush all TLBs in MP\n");
+            warn_once("Need to flush all TLBs in MP\n");
             tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
             tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
             return;

diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 0b29a8270e93b79d5ac2b155fb2818168c1ec77e..b529fdfd49ea5cec01d2da06f453d65eee14576d 100644 (file)
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -100,7 +100,7 @@ class RealViewPBX(RealView):
     timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
     timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
 
-    l2x0_fake     = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
+    l2x0_fake     = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
     flash_fake    = IsaFake(pio_addr=0x40000000, pio_size=0x4000000)
     dmac_fake     = AmbaFake(pio_addr=0x10030000)
     uart1_fake    = AmbaFake(pio_addr=0x1000a000)