[ARC] Update disassembler opcode selection

New instruction are added, and some of them are overlapping. Update
disassembler to correctly recognize them. Introduce nps400 option.

opcodes/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
	and MPY class instructions.
	(parse_option): Add nps400 option.
	(print_arc_disassembler_options): Add nps400 info.

gas/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/nps400-6.d: Update test.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index c08ccbc9b60ecbb8bba6e58c22f139ca97dbb26a..ab519fa40350d8a4cc2de19c964dfc00fb6a8e84 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * testsuite/gas/arc/nps400-6.d: Update test.
+
 2019-07-24  Alan Modra  <amodra@gmail.com>
 
        * config/obj-elf.c (obj_elf_section, obj_elf_type): Set has_gnu_osabi.

diff --git a/gas/testsuite/gas/arc/nps400-6.d b/gas/testsuite/gas/arc/nps400-6.d
index 3adf7561303f0888af1869e79ee6ca1fdb4dfd29..95344082bfde5010d90fe672288466b947dbf1f6 100644 (file)
--- a/gas/testsuite/gas/arc/nps400-6.d
+++ b/gas/testsuite/gas/arc/nps400-6.d
@@ -1,5 +1,5 @@
 #as: -mcpu=arc700 -mnps400
-#objdump: -dr
+#objdump: -dr -Mnps400
 
 .*: +file format .*arc.*
 

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e0e6bdb4d91a1e56190d03ded18b392777bdcf1d..ba0be867046cdf9c198f992fb00c6d9597b5c2c2 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
+       and MPY class instructions.
+       (parse_option): Add nps400 option.
+       (print_arc_disassembler_options): Add nps400 info.
+
 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 
        * arc-ext-tbl.h (bspeek): Remove it, added to main table.

diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index ee598918c51ff7506d50d364dcdf962769af69dd..8207c05519320d315ac20fec1aa5202985a0878b 100644 (file)
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -181,7 +181,9 @@ skip_this_opcode (const struct arc_opcode *opcode)
 
   /* Check opcode for major 0x06, return if it is not in.  */
   if (arc_opcode_len (opcode) == 4
-      && OPCODE_32BIT_INSN (opcode->opcode) != 0x06)
+      && (OPCODE_32BIT_INSN (opcode->opcode) != 0x06
+         /* Can be an APEX extensions.  */
+         && OPCODE_32BIT_INSN (opcode->opcode) != 0x07))
     return FALSE;
 
   /* or not a known truble class.  */
@@ -190,6 +192,7 @@ skip_this_opcode (const struct arc_opcode *opcode)
     case FLOAT:
     case DSP:
     case ARITH:
+    case MPY:
       break;
     default:
       return FALSE;
@@ -764,6 +767,23 @@ parse_option (const char *option)
   else if (disassembler_options_cmp (option, "fpuda") == 0)
     add_to_decodelist (FLOAT, DPA);
 
+  else if (disassembler_options_cmp (option, "nps400") == 0)
+    {
+      add_to_decodelist (ACL, NPS400);
+      add_to_decodelist (ARITH, NPS400);
+      add_to_decodelist (BITOP, NPS400);
+      add_to_decodelist (BMU, NPS400);
+      add_to_decodelist (CONTROL, NPS400);
+      add_to_decodelist (DMA, NPS400);
+      add_to_decodelist (DPI, NPS400);
+      add_to_decodelist (MEMORY, NPS400);
+      add_to_decodelist (MISC, NPS400);
+      add_to_decodelist (NET, NPS400);
+      add_to_decodelist (PMU, NPS400);
+      add_to_decodelist (PROTOCOL_DECODE, NPS400);
+      add_to_decodelist (ULTRAIP, NPS400);
+    }
+
   else if (disassembler_options_cmp (option, "fpus") == 0)
     {
       add_to_decodelist (FLOAT, SP);
@@ -1411,6 +1431,8 @@ with -M switch (multiple options should be separated by commas):\n"));
   fprintf (stream, _("\
   fpud            Recognize double precision FPU instructions.\n"));
   fprintf (stream, _("\
+  nps400          Recognize NPS400 instructions.\n"));
+  fprintf (stream, _("\
   hex             Use only hexadecimal number to print immediates.\n"));
 }