(compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "x86_64_general_operand" "")))]
""
- "
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[0] = force_reg (DImode, operands[0]);
ix86_compare_op0 = operands[0];
ix86_compare_op1 = operands[1];
DONE;
-}")
+})
(define_expand "cmpsi"
[(set (reg:CC 17)
(compare:CC (match_operand:SI 0 "cmpsi_operand" "")
(match_operand:SI 1 "general_operand" "")))]
""
- "
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[0] = force_reg (SImode, operands[0]);
ix86_compare_op0 = operands[0];
ix86_compare_op1 = operands[1];
DONE;
-}")
+})
(define_expand "cmphi"
[(set (reg:CC 17)
(compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
(match_operand:HI 1 "general_operand" "")))]
""
- "
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[0] = force_reg (HImode, operands[0]);
ix86_compare_op0 = operands[0];
ix86_compare_op1 = operands[1];
DONE;
-}")
+})
(define_expand "cmpqi"
[(set (reg:CC 17)
(compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
(match_operand:QI 1 "general_operand" "")))]
"TARGET_QIMODE_MATH"
- "
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[0] = force_reg (QImode, operands[0]);
ix86_compare_op0 = operands[0];
ix86_compare_op1 = operands[1];
DONE;
-}")
+})
(define_insn "cmpdi_ccno_1_rex64"
[(set (reg 17)
(match_operand:DI 1 "const0_operand" "n,n")))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"@
- test{q}\\t{%0, %0|%0, %0}
- cmp{q}\\t{%1, %0|%0, %1}"
+ test{q}\t{%0, %0|%0, %0}
+ cmp{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "test,icmp")
(set_attr "length_immediate" "0,1")
(set_attr "mode" "DI")])
(match_operand:DI 1 "x86_64_general_operand" "re,mr"))
(const_int 0)))]
"ix86_match_ccmode (insn, CCGOCmode)"
- "cmp{q}\\t{%1, %0|%0, %1}"
+ "cmp{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "icmp")
(set_attr "mode" "DI")])
(compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
(match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
- "cmp{q}\\t{%1, %0|%0, %1}"
+ "cmp{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "icmp")
(set_attr "mode" "DI")])
(match_operand:SI 1 "const0_operand" "n,n")))]
"ix86_match_ccmode (insn, CCNOmode)"
"@
- test{l}\\t{%0, %0|%0, %0}
- cmp{l}\\t{%1, %0|%0, %1}"
+ test{l}\t{%0, %0|%0, %0}
+ cmp{l}\t{%1, %0|%0, %1}"
[(set_attr "type" "test,icmp")
(set_attr "length_immediate" "0,1")
(set_attr "mode" "SI")])
(match_operand:SI 1 "general_operand" "ri,mr"))
(const_int 0)))]
"ix86_match_ccmode (insn, CCGOCmode)"
- "cmp{l}\\t{%1, %0|%0, %1}"
+ "cmp{l}\t{%1, %0|%0, %1}"
[(set_attr "type" "icmp")
(set_attr "mode" "SI")])
(match_operand:SI 1 "general_operand" "ri,mr")))]
"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& ix86_match_ccmode (insn, CCmode)"
- "cmp{l}\\t{%1, %0|%0, %1}"
+ "cmp{l}\t{%1, %0|%0, %1}"
[(set_attr "type" "icmp")
(set_attr "mode" "SI")])
(match_operand:HI 1 "const0_operand" "n,n")))]
"ix86_match_ccmode (insn, CCNOmode)"
"@
- test{w}\\t{%0, %0|%0, %0}
- cmp{w}\\t{%1, %0|%0, %1}"
+ test{w}\t{%0, %0|%0, %0}
+ cmp{w}\t{%1, %0|%0, %1}"
[(set_attr "type" "test,icmp")
(set_attr "length_immediate" "0,1")
(set_attr "mode" "HI")])
(match_operand:HI 1 "general_operand" "ri,mr"))
(const_int 0)))]
"ix86_match_ccmode (insn, CCGOCmode)"
- "cmp{w}\\t{%1, %0|%0, %1}"
+ "cmp{w}\t{%1, %0|%0, %1}"
[(set_attr "type" "icmp")
(set_attr "mode" "HI")])
(match_operand:HI 1 "general_operand" "ri,mr")))]
"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& ix86_match_ccmode (insn, CCmode)"
- "cmp{w}\\t{%1, %0|%0, %1}"
+ "cmp{w}\t{%1, %0|%0, %1}"
[(set_attr "type" "icmp")
(set_attr "mode" "HI")])
(match_operand:QI 1 "const0_operand" "n,n")))]
"ix86_match_ccmode (insn, CCNOmode)"
"@
- test{b}\\t{%0, %0|%0, %0}
- cmp{b}\\t{$0, %0|%0, 0}"
+ test{b}\t{%0, %0|%0, %0}
+ cmp{b}\t{$0, %0|%0, 0}"
[(set_attr "type" "test,icmp")
(set_attr "length_immediate" "0,1")
(set_attr "mode" "QI")])
(match_operand:QI 1 "general_operand" "qi,mq")))]
"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& ix86_match_ccmode (insn, CCmode)"
- "cmp{b}\\t{%1, %0|%0, %1}"
+ "cmp{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "icmp")
(set_attr "mode" "QI")])
(match_operand:QI 1 "general_operand" "qi,mq"))
(const_int 0)))]
"ix86_match_ccmode (insn, CCGOCmode)"
- "cmp{b}\\t{%1, %0|%0, %1}"
+ "cmp{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "icmp")
(set_attr "mode" "QI")])
(const_int 8)
(const_int 8)) 0)))]
"!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
- "cmp{b}\\t{%h1, %0|%0, %h1}"
+ "cmp{b}\t{%h1, %0|%0, %h1}"
[(set_attr "type" "icmp")
(set_attr "mode" "QI")])
(const_int 8)
(const_int 8)) 0)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
- "cmp{b}\\t{%h1, %0|%0, %h1}"
+ "cmp{b}\t{%h1, %0|%0, %h1}"
[(set_attr "type" "icmp")
(set_attr "mode" "QI")])
(const_int 8)) 0)
(match_operand:QI 1 "const0_operand" "n")))]
"ix86_match_ccmode (insn, CCNOmode)"
- "test{b}\\t%h0, %h0"
+ "test{b}\t%h0, %h0"
[(set_attr "type" "test")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
(const_int 8)) 0)
(match_operand:QI 1 "general_operand" "Qmn")))]
"!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
- "cmp{b}\\t{%1, %h0|%h0, %1}"
+ "cmp{b}\t{%1, %h0|%h0, %1}"
[(set_attr "type" "icmp")
(set_attr "mode" "QI")])
(const_int 8)) 0)
(match_operand:QI 1 "nonmemory_operand" "Qn")))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
- "cmp{b}\\t{%1, %h0|%h0, %1}"
+ "cmp{b}\t{%1, %h0|%h0, %1}"
[(set_attr "type" "icmp")
(set_attr "mode" "QI")])
(const_int 8)
(const_int 8)) 0)))]
"ix86_match_ccmode (insn, CCmode)"
- "cmp{b}\\t{%h1, %h0|%h0, %h1}"
+ "cmp{b}\t{%h1, %h0|%h0, %h1}"
[(set_attr "type" "icmp")
(set_attr "mode" "QI")])
(compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
(match_operand:XF 1 "cmp_fp_expander_operand" "")))]
"TARGET_80387 && !TARGET_64BIT"
- "
{
ix86_compare_op0 = operands[0];
ix86_compare_op1 = operands[1];
DONE;
-}")
+})
(define_expand "cmptf"
[(set (reg:CC 17)
(compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
(match_operand:TF 1 "cmp_fp_expander_operand" "")))]
"TARGET_80387"
- "
{
ix86_compare_op0 = operands[0];
ix86_compare_op1 = operands[1];
DONE;
-}")
+})
(define_expand "cmpdf"
[(set (reg:CC 17)
(compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
(match_operand:DF 1 "cmp_fp_expander_operand" "")))]
"TARGET_80387 || TARGET_SSE2"
- "
{
ix86_compare_op0 = operands[0];
ix86_compare_op1 = operands[1];
DONE;
-}")
+})
(define_expand "cmpsf"
[(set (reg:CC 17)
(compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
(match_operand:SF 1 "cmp_fp_expander_operand" "")))]
"TARGET_80387 || TARGET_SSE"
- "
{
ix86_compare_op0 = operands[0];
ix86_compare_op1 = operands[1];
DONE;
-}")
+})
;; FP compares, step 1:
;; Set the FP condition codes.
"TARGET_80387
&& FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])"
- "*
{
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"ftst\;fnstsw\\t%0\;fstp\\t%y0\";
+ return "ftst\;fnstsw\t%0\;fstp\t%y0";
else
- return \"ftst\;fnstsw\\t%0\";
-}"
+ return "ftst\;fnstsw\t%0";
+}
[(set_attr "type" "multi")
(set_attr "mode" "unknownfp")])
[(set (match_operand:HI 0 "register_operand" "=a")
(unspec:HI [(reg 18)] 9))]
"TARGET_80387"
- "fnstsw\\t%0"
+ "fnstsw\t%0"
[(set_attr "length" "2")
(set_attr "mode" "SI")
(set_attr "i387" "1")
[(set (match_operand:SI 0 "push_operand" "=<")
(match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
"!TARGET_64BIT"
- "push{l}\\t%1"
+ "push{l}\t%1"
[(set_attr "type" "push")
(set_attr "mode" "SI")])
[(set (match_operand:SI 0 "push_operand" "=X")
(match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
"TARGET_64BIT"
- "push{q}\\t%q1"
+ "push{q}\t%q1"
[(set_attr "type" "push")
(set_attr "mode" "SI")])
(match_operand:SI 1 "general_no_elim_operand" "ri*m"))
(clobber (mem:BLK (scratch)))]
"!TARGET_64BIT"
- "push{l}\\t%1"
+ "push{l}\t%1"
[(set_attr "type" "push")
(set_attr "mode" "SI")])
(plus:SI (reg:SI 7) (const_int 4)))
(clobber (mem:BLK (scratch)))]
"!TARGET_64BIT"
- "pop{l}\\t%0"
+ "pop{l}\t%0"
[(set_attr "type" "pop")
(set_attr "mode" "SI")])
(set (reg:SI 7)
(plus:SI (reg:SI 7) (const_int 4)))]
"!TARGET_64BIT"
- "pop{l}\\t%0"
+ "pop{l}\t%0"
[(set_attr "type" "pop")
(set_attr "mode" "SI")])
(match_operand:SI 1 "const0_operand" "i"))
(clobber (reg:CC 17))]
"reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
- "xor{l}\\t{%0, %0|%0, %0}"
+ "xor{l}\t{%0, %0|%0, %0}"
[(set_attr "type" "alu1")
(set_attr "mode" "SI")
(set_attr "length_immediate" "0")])
"reload_completed && GET_CODE (operands[1]) == CONST_INT
&& INTVAL (operands[1]) == -1
&& (TARGET_PENTIUM || optimize_size)"
- "*
{
operands[1] = constm1_rtx;
- return \"or{l}\\t{%1, %0|%0, %1}\";
-}"
+ return "or{l}\t{%1, %0|%0, %1}";
+}
[(set_attr "type" "alu1")
(set_attr "mode" "SI")
(set_attr "length_immediate" "1")])
[(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!rm,!*Y,!rm,!*Y")
(match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,rm,*Y,*Y"))]
"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_SSE:
if (get_attr_mode (insn) == TImode)
- return \"movdqa\\t{%1, %0|%0, %1}\";
- return \"movd\\t{%1, %0|%0, %1}\";
+ return "movdqa\t{%1, %0|%0, %1}";
+ return "movd\t{%1, %0|%0, %1}";
case TYPE_MMX:
- return \"movd\\t{%1, %0|%0, %1}\";
+ return "movd\t{%1, %0|%0, %1}";
case TYPE_LEA:
- return \"lea{l}\\t{%1, %0|%0, %1}\";
+ return "lea{l}\t{%1, %0|%0, %1}";
default:
if (flag_pic && SYMBOLIC_CONST (operands[1]))
abort();
- return \"mov{l}\\t{%1, %0|%0, %1}\";
+ return "mov{l}\t{%1, %0|%0, %1}";
}
-}"
+}
[(set (attr "type")
(cond [(eq_attr "alternative" "4,5")
(const_string "mmx")
(match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
"TARGET_64BIT"
"@
- movabs{l}\\t{%1, %P0|%P0, %1}
- mov{l}\\t{%1, %a0|%a0, %1}
- movabs{l}\\t{%1, %a0|%a0, %1}"
+ movabs{l}\t{%1, %P0|%P0, %1}
+ mov{l}\t{%1, %a0|%a0, %1}
+ movabs{l}\t{%1, %a0|%a0, %1}"
[(set_attr "type" "imov")
(set_attr "modrm" "0,*,*")
(set_attr "length_address" "8,0,0")
(mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
"TARGET_64BIT"
"@
- movabs{l}\\t{%P1, %0|%0, %P1}
- mov{l}\\t{%a1, %0|%0, %a1}"
+ movabs{l}\t{%P1, %0|%0, %P1}
+ mov{l}\t{%a1, %0|%0, %a1}"
[(set_attr "type" "imov")
(set_attr "modrm" "0,*")
(set_attr "length_address" "8,0")
(set (match_dup 1)
(match_dup 0))]
""
- "xchg{l}\\t%1, %0"
+ "xchg{l}\t%1, %0"
[(set_attr "type" "imov")
(set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")
(match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
"!TARGET_64BIT"
"@
- push{w}\\t{|WORD PTR }%1
- push{w}\\t%1"
+ push{w}\t{|WORD PTR }%1
+ push{w}\t%1"
[(set_attr "type" "push")
(set_attr "mode" "HI")])
[(set (match_operand:HI 0 "push_operand" "=X")
(match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
"TARGET_64BIT"
- "push{q}\\t%q1"
+ "push{q}\t%q1"
[(set_attr "type" "push")
(set_attr "mode" "QI")])
[(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
(match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_IMOVX:
/* movzwl is faster than movw on p2 due to partial word stalls,
though not as fast as an aligned movl. */
- return \"movz{wl|x}\\t{%1, %k0|%k0, %1}\";
+ return "movz{wl|x}\t{%1, %k0|%k0, %1}";
default:
if (get_attr_mode (insn) == MODE_SI)
- return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
+ return "mov{l}\t{%k1, %k0|%k0, %k1}";
else
- return \"mov{w}\\t{%1, %0|%0, %1}\";
+ return "mov{w}\t{%1, %0|%0, %1}";
}
-}"
+}
[(set (attr "type")
(cond [(and (eq_attr "alternative" "0,1")
(ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
(match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
"TARGET_64BIT"
"@
- movabs{w}\\t{%1, %P0|%P0, %1}
- mov{w}\\t{%1, %a0|%a0, %1}
- movabs{w}\\t{%1, %a0|%a0, %1}"
+ movabs{w}\t{%1, %P0|%P0, %1}
+ mov{w}\t{%1, %a0|%a0, %1}
+ movabs{w}\t{%1, %a0|%a0, %1}"
[(set_attr "type" "imov")
(set_attr "modrm" "0,*,*")
(set_attr "length_address" "8,0,0")
(mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
"TARGET_64BIT"
"@
- movabs{w}\\t{%P1, %0|%0, %P1}
- mov{w}\\t{%a1, %0|%0, %a1}"
+ movabs{w}\t{%P1, %0|%0, %P1}
+ mov{w}\t{%a1, %0|%0, %a1}"
[(set_attr "type" "imov")
(set_attr "modrm" "0,*")
(set_attr "length_address" "8,0")
(set (match_dup 1)
(match_dup 0))]
"TARGET_PARTIAL_REG_STALL"
- "xchg{w}\\t%1, %0"
+ "xchg{w}\t%1, %0"
[(set_attr "type" "imov")
(set_attr "pent_pair" "np")
(set_attr "mode" "HI")
(set (match_dup 1)
(match_dup 0))]
"! TARGET_PARTIAL_REG_STALL"
- "xchg{l}\\t%k1, %k0"
+ "xchg{l}\t%k1, %k0"
[(set_attr "type" "imov")
(set_attr "pent_pair" "np")
(set_attr "mode" "SI")
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
(match_operand:HI 1 "general_operand" ""))]
"! TARGET_PARTIAL_REG_STALL || optimize_size"
- "
{
/* Don't generate memory->memory moves, go through a register */
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[1] = force_reg (HImode, operands[1]);
-}")
+})
(define_insn "*movstricthi_1"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
(match_operand:HI 1 "general_operand" "rn,m"))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "mov{w}\\t{%1, %0|%0, %1}"
+ "mov{w}\t{%1, %0|%0, %1}"
[(set_attr "type" "imov")
(set_attr "mode" "HI")])
(clobber (reg:CC 17))]
"reload_completed
&& ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
- "xor{w}\\t{%0, %0|%0, %0}"
+ "xor{w}\t{%0, %0|%0, %0}"
[(set_attr "type" "alu1")
(set_attr "mode" "HI")
(set_attr "length_immediate" "0")])
(match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
"!TARGET_64BIT"
"@
- push{w}\\t{|word ptr }%1
- push{w}\\t%w1"
+ push{w}\t{|word ptr }%1
+ push{w}\t%w1"
[(set_attr "type" "push")
(set_attr "mode" "HI")])
[(set (match_operand:QI 0 "push_operand" "=X")
(match_operand:QI 1 "nonmemory_no_elim_operand" "ri"))]
"TARGET_64BIT"
- "push{q}\\t%q1"
+ "push{q}\t%q1"
[(set_attr "type" "push")
(set_attr "mode" "QI")])
[(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
(match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_IMOVX:
if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
abort ();
- return \"movz{bl|x}\\t{%1, %k0|%k0, %1}\";
+ return "movz{bl|x}\t{%1, %k0|%k0, %1}";
default:
if (get_attr_mode (insn) == MODE_SI)
- return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
+ return "mov{l}\t{%k1, %k0|%k0, %k1}";
else
- return \"mov{b}\\t{%1, %0|%0, %1}\";
+ return "mov{b}\t{%1, %0|%0, %1}";
}
-}"
+}
[(set (attr "type")
(cond [(and (eq_attr "alternative" "3")
(ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
(match_operand:QI 1 "register_operand" "r")
(match_operand:QI 2 "register_operand" "=&q")])]
""
- "
{
rtx op0, op1, op2;
op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
}
emit_insn (gen_movqi (op0, op1));
DONE;
-}")
+})
(define_insn "*swapqi"
[(set (match_operand:QI 0 "register_operand" "+r")
(set (match_dup 1)
(match_dup 0))]
""
- "xchg{b}\\t%1, %0"
+ "xchg{b}\t%1, %0"
[(set_attr "type" "imov")
(set_attr "pent_pair" "np")
(set_attr "mode" "QI")
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
(match_operand:QI 1 "general_operand" ""))]
"! TARGET_PARTIAL_REG_STALL"
- "
{
/* Don't generate memory->memory moves, go through a register */
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[1] = force_reg (QImode, operands[1]);
-}")
+})
(define_insn "*movstrictqi_1"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
(match_operand:QI 1 "general_operand" "*qn,m"))]
"! TARGET_PARTIAL_REG_STALL
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "mov{b}\\t{%1, %0|%0, %1}"
+ "mov{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "imov")
(set_attr "mode" "QI")])
(match_operand:QI 1 "const0_operand" "i"))
(clobber (reg:CC 17))]
"reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
- "xor{b}\\t{%0, %0|%0, %0}"
+ "xor{b}\t{%0, %0|%0, %0}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")
(set_attr "length_immediate" "0")])
(const_int 8)
(const_int 8)))]
""
- "movs{bl|x}\\t{%h1, %0|%0, %h1}"
+ "movs{bl|x}\t{%h1, %0|%0, %h1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
(const_int 8)
(const_int 8)))]
""
- "movs{bl|x}\\t{%h1, %k0|%k0, %h1}"
+ "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
(const_int 8)
(const_int 8)))]
"!TARGET_64BIT"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_IMOVX:
- return \"movs{bl|x}\\t{%h1, %k0|%k0, %h1}\";
+ return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
default:
- return \"mov{b}\\t{%h1, %0|%0, %h1}\";
+ return "mov{b}\t{%h1, %0|%0, %h1}";
}
-}"
+}
[(set (attr "type")
(if_then_else (and (match_operand:QI 0 "register_operand" "")
(ior (not (match_operand:QI 0 "q_regs_operand" ""))
(const_int 8)
(const_int 8)))]
"TARGET_64BIT"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_IMOVX:
- return \"movs{bl|x}\\t{%h1, %k0|%k0, %h1}\";
+ return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
default:
- return \"mov{b}\\t{%h1, %0|%0, %h1}\";
+ return "mov{b}\t{%h1, %0|%0, %h1}";
}
-}"
+}
[(set (attr "type")
(if_then_else (and (match_operand:QI 0 "register_operand" "")
(ior (not (match_operand:QI 0 "q_regs_operand" ""))
(match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
"TARGET_64BIT"
"@
- movabs{q}\\t{%1, %P0|%P0, %1}
- mov{q}\\t{%1, %a0|%a0, %1}
- movabs{q}\\t{%1, %a0|%a0, %1}"
+ movabs{q}\t{%1, %P0|%P0, %1}
+ mov{q}\t{%1, %a0|%a0, %1}
+ movabs{q}\t{%1, %a0|%a0, %1}"
[(set_attr "type" "imov")
(set_attr "modrm" "0,*,*")
(set_attr "length_address" "8,0,0")
(mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
"TARGET_64BIT"
"@
- movabs{q}\\t{%P1, %0|%0, %P1}
- mov{q}\\t{%a1, %0|%0, %a1}"
+ movabs{q}\t{%P1, %0|%0, %P1}
+ mov{q}\t{%a1, %0|%0, %a1}"
[(set_attr "type" "imov")
(set_attr "modrm" "0,*")
(set_attr "length_address" "8,0")
(const_int 8)
(const_int 8)))]
""
- "movz{bl|x}\\t{%h1, %0|%0, %h1}"
+ "movz{bl|x}\t{%h1, %0|%0, %h1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
(const_int 8)
(const_int 8)) 0))]
"!TARGET_64BIT"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_IMOVX:
- return \"movz{bl|x}\\t{%h1, %k0|%k0, %h1}\";
+ return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
default:
- return \"mov{b}\\t{%h1, %0|%0, %h1}\";
+ return "mov{b}\t{%h1, %0|%0, %h1}";
}
-}"
+}
[(set (attr "type")
(if_then_else (and (match_operand:QI 0 "register_operand" "")
(ior (not (match_operand:QI 0 "q_regs_operand" ""))
(const_int 8)
(const_int 8)) 0))]
"TARGET_64BIT"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_IMOVX:
- return \"movz{bl|x}\\t{%h1, %k0|%k0, %h1}\";
+ return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
default:
- return \"mov{b}\\t{%h1, %0|%0, %h1}\";
+ return "mov{b}\t{%h1, %0|%0, %h1}";
}
-}"
+}
[(set (attr "type")
(if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
(ne (symbol_ref "TARGET_MOVX")
(const_int 8))
(match_operand:SI 1 "general_operand" "Qmn"))]
"!TARGET_64BIT"
- "mov{b}\\t{%b1, %h0|%h0, %b1}"
+ "mov{b}\t{%b1, %h0|%h0, %b1}"
[(set_attr "type" "imov")
(set_attr "mode" "QI")])
(const_int 8))
(match_operand:SI 1 "nonmemory_operand" "Qn"))]
"TARGET_64BIT"
- "mov{b}\\t{%b1, %h0|%h0, %b1}"
+ "mov{b}\t{%b1, %h0|%h0, %b1}"
[(set_attr "type" "imov")
(set_attr "mode" "QI")])
(const_int 8))
(const_int 255)))]
""
- "mov{b}\\t{%h1, %h0|%h0, %h1}"
+ "mov{b}\t{%h1, %h0|%h0, %h1}"
[(set_attr "type" "imov")
(set_attr "mode" "QI")])
(match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
"TARGET_64BIT"
"@
- push{q}\\t%1
+ push{q}\t%1
#"
[(set_attr "type" "push,multi")
(set_attr "mode" "DI")])
(match_operand:DI 1 "general_no_elim_operand" "re*m"))
(clobber (mem:BLK (scratch)))]
"TARGET_64BIT"
- "push{q}\\t%1"
+ "push{q}\t%1"
[(set_attr "type" "push")
(set_attr "mode" "DI")])
(plus:DI (reg:DI 7) (const_int 8)))
(clobber (mem:BLK (scratch)))]
"TARGET_64BIT"
- "pop{q}\\t%0"
+ "pop{q}\t%0"
[(set_attr "type" "pop")
(set_attr "mode" "DI")])
(set (reg:DI 7)
(plus:DI (reg:DI 7) (const_int 8)))]
"TARGET_64BIT"
- "pop{q}\\t%0"
+ "pop{q}\t%0"
[(set_attr "type" "pop")
(set_attr "mode" "DI")])
(clobber (reg:CC 17))]
"reload_completed && (!TARGET_USE_MOV0 || optimize_size)
&& TARGET_64BIT"
- "xor{l}\\t{%k0, %k0|%k0, %k0}"
+ "xor{l}\t{%k0, %k0|%k0, %k0}"
[(set_attr "type" "alu1")
(set_attr "mode" "SI")
(set_attr "length_immediate" "0")])
&& TARGET_64BIT
&& INTVAL (operands[1]) == -1
&& (TARGET_PENTIUM || optimize_size)"
- "*
{
operands[1] = constm1_rtx;
- return \"or{q}\\t{%1, %0|%0, %1}\";
-}"
+ return "or{q}\t{%1, %0|%0, %1}";
+}
[(set_attr "type" "alu1")
(set_attr "mode" "DI")
(set_attr "length_immediate" "1")])
"@
#
#
- movq\\t{%1, %0|%0, %1}
- movq\\t{%1, %0|%0, %1}
- movq\\t{%1, %0|%0, %1}
- movdqa\\t{%1, %0|%0, %1}
- movq\\t{%1, %0|%0, %1}"
+ movq\t{%1, %0|%0, %1}
+ movq\t{%1, %0|%0, %1}
+ movq\t{%1, %0|%0, %1}
+ movdqa\t{%1, %0|%0, %1}
+ movq\t{%1, %0|%0, %1}"
[(set_attr "type" "*,*,mmx,mmx,sse,sse,sse")
(set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
(match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*Y,*m"))]
"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& TARGET_64BIT"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_SSE:
if (register_operand (operands[0], DImode)
&& register_operand (operands[1], DImode))
- return \"movdqa\\t{%1, %0|%0, %1}\";
+ return "movdqa\t{%1, %0|%0, %1}";
/* FALLTHRU */
case TYPE_MMX:
- return \"movq\\t{%1, %0|%0, %1}\";
+ return "movq\t{%1, %0|%0, %1}";
case TYPE_MULTI:
- return \"#\";
+ return "#";
case TYPE_LEA:
- return \"lea{q}\\t{%a1, %0|%0, %a1}\";
+ return "lea{q}\t{%a1, %0|%0, %a1}";
default:
if (flag_pic && SYMBOLIC_CONST (operands[1]))
abort ();
if (get_attr_mode (insn) == MODE_SI)
- return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
+ return "mov{l}\t{%k1, %k0|%k0, %k1}";
else if (which_alternative == 2)
- return \"movabs{q}\\t{%1, %0|%0, %1}\";
+ return "movabs{q}\t{%1, %0|%0, %1}";
else
- return \"mov{q}\\t{%1, %0|%0, %1}\";
+ return "mov{q}\t{%1, %0|%0, %1}";
}
-}"
+}
[(set (attr "type")
(cond [(eq_attr "alternative" "5,6")
(const_string "mmx")
(match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
"TARGET_64BIT"
"@
- movabs{q}\\t{%1, %P0|%P0, %1}
- mov{q}\\t{%1, %a0|%a0, %1}
- movabs{q}\\t{%1, %a0|%a0, %1}"
+ movabs{q}\t{%1, %P0|%P0, %1}
+ mov{q}\t{%1, %a0|%a0, %1}
+ movabs{q}\t{%1, %a0|%a0, %1}"
[(set_attr "type" "imov")
(set_attr "modrm" "0,*,*")
(set_attr "length_address" "8,0,0")
(mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
"TARGET_64BIT"
"@
- movabs{q}\\t{%P1, %0|%0, %P1}
- mov{q}\\t{%a1, %0|%0, %a1}"
+ movabs{q}\t{%P1, %0|%0, %P1}
+ mov{q}\t{%a1, %0|%0, %a1}"
[(set_attr "type" "imov")
(set_attr "modrm" "0,*")
(set_attr "length_address" "8,0")
(set (match_dup 1)
(match_dup 0))]
"TARGET_64BIT"
- "xchg{q}\\t%1, %0"
+ "xchg{q}\t%1, %0"
[(set_attr "type" "imov")
(set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")
[(set (match_operand:SF 0 "push_operand" "=<,<,<")
(match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
"!TARGET_64BIT"
- "*
{
switch (which_alternative)
{
operands[2] = stack_pointer_rtx;
operands[3] = GEN_INT (4);
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
+ return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
else
- return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
+ return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
case 1:
- return \"push{l}\\t%1\";
+ return "push{l}\t%1";
case 2:
- return \"#\";
+ return "#";
default:
abort ();
}
-}"
+}
[(set_attr "type" "multi,push,multi")
(set_attr "mode" "SF,SI,SF")])
[(set (match_operand:SF 0 "push_operand" "=X,X,X")
(match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
"TARGET_64BIT"
- "*
{
switch (which_alternative)
{
operands[2] = stack_pointer_rtx;
operands[3] = GEN_INT (8);
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
+ return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
else
- return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
+ return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
case 1:
- return \"push{q}\\t%q1\";
+ return "push{q}\t%q1";
case 2:
- return \"#\";
+ return "#";
default:
abort ();
}
-}"
+}
[(set_attr "type" "multi,push,multi")
(set_attr "mode" "SF,DI,SF")])
&& (reload_in_progress || reload_completed
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], SFmode))"
- "*
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp\\t%y0\";
+ return "fstp\t%y0";
else if (STACK_TOP_P (operands[0]))
- return \"fld%z1\\t%y1\";
+ return "fld%z1\t%y1";
else
- return \"fst\\t%y0\";
+ return "fst\t%y0";
case 1:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
+ return "fst%z0\t%y0";
case 2:
switch (standard_80387_constant_p (operands[1]))
{
case 1:
- return \"fldz\";
+ return "fldz";
case 2:
- return \"fld1\";
+ return "fld1";
}
abort();
case 3:
case 4:
- return \"mov{l}\\t{%1, %0|%0, %1}\";
+ return "mov{l}\t{%1, %0|%0, %1}";
case 5:
- return \"pxor\\t%0, %0\";
+ return "pxor\t%0, %0";
case 6:
if (TARGET_PARTIAL_REG_DEPENDENCY)
- return \"movaps\\t{%1, %0|%0, %1}\";
+ return "movaps\t{%1, %0|%0, %1}";
else
- return \"movss\\t{%1, %0|%0, %1}\";
+ return "movss\t{%1, %0|%0, %1}";
case 7:
case 8:
- return \"movss\\t{%1, %0|%0, %1}\";
+ return "movss\t{%1, %0|%0, %1}";
default:
abort();
}
-}"
+}
[(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse")
(set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")])
(set (match_dup 1)
(match_dup 0))]
"reload_completed || !TARGET_SSE2"
- "*
{
if (STACK_TOP_P (operands[0]))
- return \"fxch\\t%1\";
+ return "fxch\t%1";
else
- return \"fxch\\t%0\";
-}"
+ return "fxch\t%0";
+}
[(set_attr "type" "fxch")
(set_attr "mode" "SF")])
[(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
(match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
"!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
- "*
{
switch (which_alternative)
{
operands[2] = stack_pointer_rtx;
operands[3] = GEN_INT (8);
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
+ return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
else
- return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
+ return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
case 1:
case 2:
case 3:
- return \"#\";
+ return "#";
default:
abort ();
}
-}"
+}
[(set_attr "type" "multi")
(set_attr "mode" "DF,SI,SI,DF")])
[(set (match_operand:DF 0 "push_operand" "=<,<,<")
(match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
"TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
- "*
{
switch (which_alternative)
{
operands[3] = GEN_INT (8);
if (TARGET_64BIT)
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
+ return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
else
- return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
+ return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
else
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
+ return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
else
- return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
+ return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
case 1:
case 2:
- return \"#\";
+ return "#";
default:
abort ();
}
-}"
+}
[(set_attr "type" "multi")
(set_attr "mode" "DF,SI,DF")])
&& (reload_in_progress || reload_completed
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], DFmode))"
- "*
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp\\t%y0\";
+ return "fstp\t%y0";
else if (STACK_TOP_P (operands[0]))
- return \"fld%z1\\t%y1\";
+ return "fld%z1\t%y1";
else
- return \"fst\\t%y0\";
+ return "fst\t%y0";
case 1:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
+ return "fst%z0\t%y0";
case 2:
switch (standard_80387_constant_p (operands[1]))
{
case 1:
- return \"fldz\";
+ return "fldz";
case 2:
- return \"fld1\";
+ return "fld1";
}
abort();
case 3:
case 4:
- return \"#\";
+ return "#";
case 5:
- return \"pxor\\t%0, %0\";
+ return "pxor\t%0, %0";
case 6:
if (TARGET_PARTIAL_REG_DEPENDENCY)
- return \"movapd\\t{%1, %0|%0, %1}\";
+ return "movapd\t{%1, %0|%0, %1}";
else
- return \"movsd\\t{%1, %0|%0, %1}\";
+ return "movsd\t{%1, %0|%0, %1}";
case 7:
case 8:
- return \"movsd\\t{%1, %0|%0, %1}\";
+ return "movsd\t{%1, %0|%0, %1}";
default:
abort();
}
-}"
+}
[(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
(set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
&& (reload_in_progress || reload_completed
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], DFmode))"
- "*
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp\\t%y0\";
+ return "fstp\t%y0";
else if (STACK_TOP_P (operands[0]))
- return \"fld%z1\\t%y1\";
+ return "fld%z1\t%y1";
else
- return \"fst\\t%y0\";
+ return "fst\t%y0";
case 1:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
+ return "fst%z0\t%y0";
case 2:
switch (standard_80387_constant_p (operands[1]))
{
case 1:
- return \"fldz\";
+ return "fldz";
case 2:
- return \"fld1\";
+ return "fld1";
}
abort();
case 3:
case 4:
- return \"#\";
+ return "#";
case 5:
- return \"pxor\\t%0, %0\";
+ return "pxor\t%0, %0";
case 6:
if (TARGET_PARTIAL_REG_DEPENDENCY)
- return \"movapd\\t{%1, %0|%0, %1}\";
+ return "movapd\t{%1, %0|%0, %1}";
else
- return \"movsd\\t{%1, %0|%0, %1}\";
+ return "movsd\t{%1, %0|%0, %1}";
case 7:
case 8:
- return \"movsd\\t{%1, %0|%0, %1}\";
+ return "movsd\t{%1, %0|%0, %1}";
default:
abort();
}
-}"
+}
[(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
(set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
(set (match_dup 1)
(match_dup 0))]
"reload_completed || !TARGET_SSE2"
- "*
{
if (STACK_TOP_P (operands[0]))
- return \"fxch\\t%1\";
+ return "fxch\t%1";
else
- return \"fxch\\t%0\";
-}"
+ return "fxch\t%0";
+}
[(set_attr "type" "fxch")
(set_attr "mode" "DF")])
[(set (match_operand:XF 0 "push_operand" "=X,X,X")
(match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
"optimize_size && !TARGET_64BIT"
- "*
{
switch (which_alternative)
{
operands[2] = stack_pointer_rtx;
operands[3] = GEN_INT (12);
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
+ return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
else
- return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
+ return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
case 1:
case 2:
- return \"#\";
+ return "#";
default:
abort ();
}
-}"
+}
[(set_attr "type" "multi")
(set_attr "mode" "XF,SI,SI")])
[(set (match_operand:TF 0 "push_operand" "=<,<,<")
(match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
"optimize_size"
- "*
{
switch (which_alternative)
{
operands[2] = stack_pointer_rtx;
operands[3] = GEN_INT (16);
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
+ return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
else
- return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
+ return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
case 1:
case 2:
- return \"#\";
+ return "#";
default:
abort ();
}
-}"
+}
[(set_attr "type" "multi")
(set_attr "mode" "XF,SI,SI")])
[(set (match_operand:XF 0 "push_operand" "=<,<")
(match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
"!optimize_size && !TARGET_64BIT"
- "*
{
switch (which_alternative)
{
operands[2] = stack_pointer_rtx;
operands[3] = GEN_INT (12);
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
+ return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
else
- return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
+ return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
case 1:
- return \"#\";
+ return "#";
default:
abort ();
}
-}"
+}
[(set_attr "type" "multi")
(set_attr "mode" "XF,SI")])
[(set (match_operand:TF 0 "push_operand" "=<,<")
(match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
"!optimize_size"
- "*
{
switch (which_alternative)
{
operands[3] = GEN_INT (16);
if (TARGET_64BIT)
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
+ return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
else
- return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
+ return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
else
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
+ return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
else
- return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
+ return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
case 1:
- return \"#\";
+ return "#";
default:
abort ();
}
-}"
+}
[(set_attr "type" "multi")
(set_attr "mode" "XF,SI")])
&& (reload_in_progress || reload_completed
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], XFmode))"
- "*
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp\\t%y0\";
+ return "fstp\t%y0";
else if (STACK_TOP_P (operands[0]))
- return \"fld%z1\\t%y1\";
+ return "fld%z1\t%y1";
else
- return \"fst\\t%y0\";
+ return "fst\t%y0";
case 1:
/* There is no non-popping store to memory for XFmode. So if
we need one, follow the store with a load. */
if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
+ return "fstp%z0\t%y0\;fld%z0\t%y0";
else
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
case 2:
switch (standard_80387_constant_p (operands[1]))
{
case 1:
- return \"fldz\";
+ return "fldz";
case 2:
- return \"fld1\";
+ return "fld1";
}
break;
case 3: case 4:
- return \"#\";
+ return "#";
}
abort();
-}"
+}
[(set_attr "type" "fmov,fmov,fmov,multi,multi")
(set_attr "mode" "XF,XF,XF,SI,SI")])
&& (reload_in_progress || reload_completed
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], TFmode))"
- "*
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp\\t%y0\";
+ return "fstp\t%y0";
else if (STACK_TOP_P (operands[0]))
- return \"fld%z1\\t%y1\";
+ return "fld%z1\t%y1";
else
- return \"fst\\t%y0\";
+ return "fst\t%y0";
case 1:
/* There is no non-popping store to memory for XFmode. So if
we need one, follow the store with a load. */
if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
+ return "fstp%z0\t%y0\;fld%z0\t%y0";
else
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
case 2:
switch (standard_80387_constant_p (operands[1]))
{
case 1:
- return \"fldz\";
+ return "fldz";
case 2:
- return \"fld1\";
+ return "fld1";
}
break;
case 3: case 4:
- return \"#\";
+ return "#";
}
abort();
-}"
+}
[(set_attr "type" "fmov,fmov,fmov,multi,multi")
(set_attr "mode" "XF,XF,XF,SI,SI")])
&& (reload_in_progress || reload_completed
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], XFmode))"
- "*
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp\\t%y0\";
+ return "fstp\t%y0";
else if (STACK_TOP_P (operands[0]))
- return \"fld%z1\\t%y1\";
+ return "fld%z1\t%y1";
else
- return \"fst\\t%y0\";
+ return "fst\t%y0";
case 1:
/* There is no non-popping store to memory for XFmode. So if
we need one, follow the store with a load. */
if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
+ return "fstp%z0\t%y0\;fld%z0\t%y0";
else
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
case 2:
switch (standard_80387_constant_p (operands[1]))
{
case 1:
- return \"fldz\";
+ return "fldz";
case 2:
- return \"fld1\";
+ return "fld1";
}
break;
case 3: case 4:
- return \"#\";
+ return "#";
}
abort();
-}"
+}
[(set_attr "type" "fmov,fmov,fmov,multi,multi")
(set_attr "mode" "XF,XF,XF,SI,SI")])
&& (reload_in_progress || reload_completed
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], TFmode))"
- "*
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp\\t%y0\";
+ return "fstp\t%y0";
else if (STACK_TOP_P (operands[0]))
- return \"fld%z1\\t%y1\";
+ return "fld%z1\t%y1";
else
- return \"fst\\t%y0\";
+ return "fst\t%y0";
case 1:
/* There is no non-popping store to memory for XFmode. So if
we need one, follow the store with a load. */
if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
+ return "fstp%z0\t%y0\;fld%z0\t%y0";
else
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
case 2:
switch (standard_80387_constant_p (operands[1]))
{
case 1:
- return \"fldz\";
+ return "fldz";
case 2:
- return \"fld1\";
+ return "fld1";
}
break;
case 3: case 4:
- return \"#\";
+ return "#";
}
abort();
-}"
+}
[(set_attr "type" "fmov,fmov,fmov,multi,multi")
(set_attr "mode" "XF,XF,XF,SI,SI")])
(set (match_dup 1)
(match_dup 0))]
""
- "*
{
if (STACK_TOP_P (operands[0]))
- return \"fxch\\t%1\";
+ return "fxch\t%1";
else
- return \"fxch\\t%0\";
-}"
+ return "fxch\t%0";
+}
[(set_attr "type" "fxch")
(set_attr "mode" "XF")])
(set (match_dup 1)
(match_dup 0))]
""
- "*
{
if (STACK_TOP_P (operands[0]))
- return \"fxch\\t%1\";
+ return "fxch\t%1";
else
- return \"fxch\\t%0\";
-}"
+ return "fxch\t%0";
+}
[(set_attr "type" "fxch")
(set_attr "mode" "XF")])
\f
[(set (match_operand:SI 0 "register_operand" "")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
""
- "
{
if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
{
emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
DONE;
}
-}")
+})
(define_insn "zero_extendhisi2_and"
[(set (match_operand:SI 0 "register_operand" "=r")
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
"!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
- "movz{wl|x}\\t{%1, %0|%0, %1}"
+ "movz{wl|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
[(set (match_operand:HI 0 "register_operand" "=r")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
"(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
- "movz{bw|x}\\t{%1, %0|%0, %1}"
+ "movz{bw|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "HI")])
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
"(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
- "movz{bl|x}\\t{%1, %0|%0, %1}"
+ "movz{bl|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
"TARGET_64BIT"
"@
- mov\\t{%k1, %k0|%k0, %k1}
+ mov\t{%k1, %k0|%k0, %k1}
#"
[(set_attr "type" "imovx,imov")
(set_attr "mode" "SI,DI")])
(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
"TARGET_64BIT"
"@
- movz{wl|x}\\t{%1, %k0|%k0, %1}
- movz{wq|x}\\t{%1, %0|%0, %1}"
+ movz{wl|x}\t{%1, %k0|%k0, %1}
+ movz{wq|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI,DI")])
(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
"TARGET_64BIT"
"@
- movz{bl|x}\\t{%1, %k0|%k0, %1}
- movz{bq|x}\\t{%1, %0|%0, %1}"
+ movz{bl|x}\t{%1, %k0|%k0, %1}
+ movz{bq|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI,DI")])
\f
(clobber (reg:CC 17))
(clobber (match_scratch:SI 2 ""))])]
""
- "
{
if (TARGET_64BIT)
{
emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
DONE;
}
-}")
+})
(define_insn "*extendsidi2_1"
[(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
"TARGET_64BIT"
"@
{cltq|cdqe}
- movs{lq|x}\\t{%1,%0|%0, %1}"
+ movs{lq|x}\t{%1,%0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "DI")
(set_attr "prefix_0f" "0")
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
"TARGET_64BIT"
- "movs{wq|x}\\t{%1,%0|%0, %1}"
+ "movs{wq|x}\t{%1,%0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "DI")])
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
"TARGET_64BIT"
- "movs{bq|x}\\t{%1,%0|%0, %1}"
+ "movs{bq|x}\t{%1,%0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "DI")])
(clobber (match_operand:SI 2 "register_operand" ""))]
"reload_completed"
[(const_int 0)]
- "
{
split_di (&operands[0], 1, &operands[3], &operands[4]);
}
emit_move_insn (operands[4], operands[2]);
DONE;
-}")
+})
;; Extend to register case. Optimize case where source and destination
;; registers match and cases where we can use cltd.
(clobber (match_scratch:SI 2 ""))]
"reload_completed"
[(const_int 0)]
- "
{
split_di (&operands[0], 1, &operands[3], &operands[4]);
emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
DONE;
-}")
+})
(define_insn "extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=*a,r")
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
""
- "*
{
switch (get_attr_prefix_0f (insn))
{
case 0:
- return \"{cwtl|cwde}\";
+ return "{cwtl|cwde}";
default:
- return \"movs{wl|x}\\t{%1,%0|%0, %1}\";
+ return "movs{wl|x}\t{%1,%0|%0, %1}";
}
-}"
+}
[(set_attr "type" "imovx")
(set_attr "mode" "SI")
(set (attr "prefix_0f")
(zero_extend:DI
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
"TARGET_64BIT"
- "*
{
switch (get_attr_prefix_0f (insn))
{
case 0:
- return \"{cwtl|cwde}\";
+ return "{cwtl|cwde}";
default:
- return \"movs{wl|x}\\t{%1,%k0|%k0, %1}\";
+ return "movs{wl|x}\t{%1,%k0|%k0, %1}";
}
-}"
+}
[(set_attr "type" "imovx")
(set_attr "mode" "SI")
(set (attr "prefix_0f")
[(set (match_operand:HI 0 "register_operand" "=*a,r")
(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
""
- "*
{
switch (get_attr_prefix_0f (insn))
{
case 0:
- return \"{cbtw|cbw}\";
+ return "{cbtw|cbw}";
default:
- return \"movs{bw|x}\\t{%1,%0|%0, %1}\";
+ return "movs{bw|x}\t{%1,%0|%0, %1}";
}
-}"
+}
[(set_attr "type" "imovx")
(set_attr "mode" "HI")
(set (attr "prefix_0f")
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
""
- "movs{bl|x}\\t{%1,%0|%0, %1}"
+ "movs{bl|x}\t{%1,%0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
(zero_extend:DI
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
"TARGET_64BIT"
- "movs{bl|x}\\t{%1,%k0|%k0, %1}"
+ "movs{bl|x}\t{%1,%k0|%k0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
\f
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
"TARGET_80387 || TARGET_SSE2"
- "
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[1] = force_reg (SFmode, operands[1]);
-}")
+})
(define_insn "*extendsfdf2_1"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
"(TARGET_80387 || TARGET_SSE2)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "*
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp\\t%y0\";
+ return "fstp\t%y0";
else if (STACK_TOP_P (operands[0]))
- return \"fld%z1\\t%y1\";
+ return "fld%z1\t%y1";
else
- return \"fst\\t%y0\";
+ return "fst\t%y0";
case 1:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
+ return "fst%z0\t%y0";
case 2:
- return \"cvtss2sd\\t{%1, %0|%0, %1}\";
+ return "cvtss2sd\t{%1, %0|%0, %1}";
default:
abort ();
}
-}"
+}
[(set_attr "type" "fmov,fmov,sse")
(set_attr "mode" "SF,XF,DF")])
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
"!TARGET_80387 && TARGET_SSE2
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "cvtss2sd\\t{%1, %0|%0, %1}"
+ "cvtss2sd\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")])
[(set (match_operand:XF 0 "nonimmediate_operand" "")
(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "")))]
"TARGET_80387 && !TARGET_64BIT"
- "
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[1] = force_reg (SFmode, operands[1]);
-}")
+})
(define_insn "*extendsfxf2_1"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
"TARGET_80387 && !TARGET_64BIT
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "*
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp\\t%y0\";
+ return "fstp\t%y0";
else if (STACK_TOP_P (operands[0]))
- return \"fld%z1\\t%y1\";
+ return "fld%z1\t%y1";
else
- return \"fst\\t%y0\";
+ return "fst\t%y0";
case 1:
/* There is no non-popping store to memory for XFmode. So if
we need one, follow the store with a load. */
if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
+ return "fstp%z0\t%y0\n\tfld%z0\t%y0";
else
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
default:
abort ();
}
-}"
+}
[(set_attr "type" "fmov")
(set_attr "mode" "SF,XF")])
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
"TARGET_80387"
- "
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[1] = force_reg (SFmode, operands[1]);
-}")
+})
(define_insn "*extendsftf2_1"
[(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
"TARGET_80387
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "*
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp\\t%y0\";
+ return "fstp\t%y0";
else if (STACK_TOP_P (operands[0]))
- return \"fld%z1\\t%y1\";
+ return "fld%z1\t%y1";
else
- return \"fst\\t%y0\";
+ return "fst\t%y0";
case 1:
/* There is no non-popping store to memory for XFmode. So if
we need one, follow the store with a load. */
if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
+ return "fstp%z0\t%y0\n\tfld%z0\t%y0";
else
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
default:
abort ();
}
-}"
+}
[(set_attr "type" "fmov")
(set_attr "mode" "SF,XF")])
[(set (match_operand:XF 0 "nonimmediate_operand" "")
(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "")))]
"TARGET_80387 && !TARGET_64BIT"
- "
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[1] = force_reg (DFmode, operands[1]);
-}")
+})
(define_insn "*extenddfxf2_1"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
"TARGET_80387 && !TARGET_64BIT
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "*
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp\\t%y0\";
+ return "fstp\t%y0";
else if (STACK_TOP_P (operands[0]))
- return \"fld%z1\\t%y1\";
+ return "fld%z1\t%y1";
else
- return \"fst\\t%y0\";
+ return "fst\t%y0";
case 1:
/* There is no non-popping store to memory for XFmode. So if
we need one, follow the store with a load. */
if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
+ return "fstp%z0\t%y0\n\tfld%z0\t%y0";
else
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
default:
abort ();
}
-}"
+}
[(set_attr "type" "fmov")
(set_attr "mode" "DF,XF")])
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
"TARGET_80387"
- "
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[1] = force_reg (DFmode, operands[1]);
-}")
+})
(define_insn "*extenddftf2_1"
[(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
"TARGET_80387
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "*
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp\\t%y0\";
+ return "fstp\t%y0";
else if (STACK_TOP_P (operands[0]))
- return \"fld%z1\\t%y1\";
+ return "fld%z1\t%y1";
else
- return \"fst\\t%y0\";
+ return "fst\t%y0";
case 1:
/* There is no non-popping store to memory for XFmode. So if
we need one, follow the store with a load. */
if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
+ return "fstp%z0\t%y0\n\tfld%z0\t%y0";
else
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
default:
abort ();
}
-}"
+}
[(set_attr "type" "fmov")
(set_attr "mode" "DF,XF")])
(match_operand:DF 1 "register_operand" "f,f,f,f")))
(clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
"TARGET_80387 && !TARGET_SSE2"
- "*
{
switch (which_alternative)
{
case 0:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
+ return "fst%z0\t%y0";
default:
abort ();
}
-}"
+}
[(set_attr "type" "fmov,multi,multi,multi")
(set_attr "mode" "SF,SF,SF,SF")])
(match_operand:DF 1 "nonimmediate_operand" "f,f,f,f,mY")))
(clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
"TARGET_80387 && TARGET_SSE2"
- "*
{
switch (which_alternative)
{
case 0:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
+ return "fst%z0\t%y0";
case 4:
- return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
+ return "cvtsd2ss\t{%1, %0|%0, %1}";
default:
abort ();
}
-}"
+}
[(set_attr "type" "fmov,multi,multi,multi,sse")
(set_attr "mode" "SF,SF,SF,SF,DF")])
(match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
"TARGET_80387 && TARGET_SSE2
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "*
{
switch (which_alternative)
{
case 0:
- return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
+ return "cvtsd2ss\t{%1, %0|%0, %1}";
case 1:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
+ return "fst%z0\t%y0";
+ default:
+ abort ();
}
-}"
+}
[(set_attr "type" "sse,fmov")
(set_attr "mode" "DF,SF")])
(float_truncate:SF
(match_operand:DF 1 "register_operand" "f")))]
"TARGET_80387"
- "*
{
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
-}"
+ return "fst%z0\t%y0";
+}
[(set_attr "type" "fmov")
(set_attr "mode" "SF")])
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "mY")))]
"!TARGET_80387 && TARGET_SSE2"
- "cvtsd2ss\\t{%1, %0|%0, %1}"
+ "cvtsd2ss\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")])
(match_operand:XF 1 "register_operand" "f,f,f,f")))
(clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
"TARGET_80387 && !TARGET_64BIT"
- "*
{
switch (which_alternative)
{
case 0:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
+ return "fst%z0\t%y0";
default:
abort();
}
-}"
+}
[(set_attr "type" "fmov,multi,multi,multi")
(set_attr "mode" "SF")])
(float_truncate:SF
(match_operand:XF 1 "register_operand" "f")))]
"TARGET_80387 && !TARGET_64BIT"
- "*
{
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
-}"
+ return "fst%z0\t%y0";
+}
[(set_attr "type" "fmov")
(set_attr "mode" "SF")])
(match_operand:TF 1 "register_operand" "f,f,f,f")))
(clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
"TARGET_80387"
- "*
{
switch (which_alternative)
{
case 0:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
+ return "fst%z0\t%y0";
default:
abort();
}
-}"
+}
[(set_attr "type" "fmov,multi,multi,multi")
(set_attr "mode" "SF")])
(float_truncate:SF
(match_operand:TF 1 "register_operand" "f")))]
"TARGET_80387"
- "*
{
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
-}"
+ return "fst%z0\t%y0";
+}
[(set_attr "type" "fmov")
(set_attr "mode" "SF")])
(match_operand:XF 1 "register_operand" "f,f,f,f")))
(clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
"TARGET_80387 && !TARGET_64BIT"
- "*
{
switch (which_alternative)
{
case 0:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
+ return "fst%z0\t%y0";
default:
abort();
}
abort ();
-}"
+}
[(set_attr "type" "fmov,multi,multi,multi")
(set_attr "mode" "DF")])
(float_truncate:DF
(match_operand:XF 1 "register_operand" "f")))]
"TARGET_80387 && !TARGET_64BIT"
- "*
{
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
-}"
+ return "fst%z0\t%y0";
+}
[(set_attr "type" "fmov")
(set_attr "mode" "DF")])
(match_operand:TF 1 "register_operand" "f,f,f,f")))
(clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
"TARGET_80387"
- "*
{
switch (which_alternative)
{
case 0:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
+ return "fst%z0\t%y0";
default:
abort();
}
abort ();
-}"
+}
[(set_attr "type" "fmov,multi,multi,multi")
(set_attr "mode" "DF")])
(float_truncate:DF
(match_operand:TF 1 "register_operand" "f")))]
"TARGET_80387"
- "*
{
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return \"fstp%z0\\t%y0\";
+ return "fstp%z0\t%y0";
else
- return \"fst%z0\\t%y0\";
-}"
+ return "fst%z0\t%y0";
+}
[(set_attr "type" "fmov")
(set_attr "mode" "DF")])
(clobber (match_dup 4))
(clobber (match_scratch:XF 5 ""))])]
"TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
- "
{
if (TARGET_SSE2 && TARGET_64BIT)
{
emit_i387_cw_initialization (operands[2], operands[3]);
operands[4] = assign_386_stack_local (DImode, 0);
}
-}")
+})
(define_expand "fix_truncsfdi2"
[(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
(clobber (match_dup 4))
(clobber (match_scratch:XF 5 ""))])]
"TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
- "
{
if (TARGET_SSE2 && TARGET_64BIT)
{
emit_i387_cw_initialization (operands[2], operands[3]);
operands[4] = assign_386_stack_local (DImode, 0);
}
-}")
+})
(define_insn "*fix_truncdi_1"
[(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
[(set (match_operand:DI 0 "register_operand" "=r")
(fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE && TARGET_64BIT"
- "cvttss2si{q}\\t{%1, %0|%0, %1}"
+ "cvttss2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "fix_truncdfdi_sse"
[(set (match_operand:DI 0 "register_operand" "=r")
(fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2 && TARGET_64BIT"
- "cvttsd2si{q}\\t{%1, %0|%0, %1}"
+ "cvttsd2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
;; Signed conversion to SImode.
(use (match_dup 3))
(clobber (match_dup 4))])]
"TARGET_80387 || TARGET_SSE2"
- "
{
if (TARGET_SSE2)
{
emit_i387_cw_initialization (operands[2], operands[3]);
operands[4] = assign_386_stack_local (SImode, 0);
}
-}")
+})
(define_expand "fix_truncsfsi2"
[(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
(use (match_dup 3))
(clobber (match_dup 4))])]
"TARGET_80387 || TARGET_SSE"
- "
{
if (TARGET_SSE2)
{
emit_i387_cw_initialization (operands[2], operands[3]);
operands[4] = assign_386_stack_local (SImode, 0);
}
-}")
+})
(define_insn "*fix_truncsi_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
[(set (match_operand:SI 0 "register_operand" "=r")
(fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
- "cvttss2si\\t{%1, %0|%0, %1}"
+ "cvttss2si\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "fix_truncdfsi_sse"
[(set (match_operand:SI 0 "register_operand" "=r")
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
- "cvttsd2si\\t{%1, %0|%0, %1}"
+ "cvttsd2si\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_split
[(set (match_operand:HI 0 "memory_operand" "=m")
(unspec:HI [(reg:HI 18)] 11))]
"TARGET_80387"
- "fnstcw\\t%0"
+ "fnstcw\t%0"
[(set_attr "length" "2")
(set_attr "mode" "HI")
(set_attr "i387" "1")
[(set (reg:HI 18)
(unspec:HI [(match_operand:HI 0 "memory_operand" "m")] 12))]
"TARGET_80387"
- "fldcw\\t%0"
+ "fldcw\t%0"
[(set_attr "length" "2")
(set_attr "mode" "HI")
(set_attr "i387" "1")
(float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
"TARGET_80387 && !TARGET_SSE"
"@
- fild%z1\\t%1
+ fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "SF")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
"TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
"@
- fild%z1\\t%1
+ fild%z1\t%1
#
- cvtsi2ss\\t{%1, %0|%0, %1}"
+ cvtsi2ss\t{%1, %0|%0, %1}"
[(set_attr "type" "fmov,multi,sse")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
[(set (match_operand:SF 0 "register_operand" "=x")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE"
- "cvtsi2ss\\t{%1, %0|%0, %1}"
+ "cvtsi2ss\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
"TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
"@
- fild%z1\\t%1
+ fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "SF")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
"TARGET_80387 && TARGET_64BIT && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
"@
- fild%z1\\t%1
+ fild%z1\t%1
#
- cvtsi2ss{q}\\t{%1, %0|%0, %1}"
+ cvtsi2ss{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "fmov,multi,sse")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
[(set (match_operand:SF 0 "register_operand" "=x")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE && TARGET_64BIT"
- "cvtsi2ss{q}\\t{%1, %0|%0, %1}"
+ "cvtsi2ss{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
(float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
"TARGET_80387 && !TARGET_SSE2"
"@
- fild%z1\\t%1
+ fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "DF")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
"TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
"@
- fild%z1\\t%1
+ fild%z1\t%1
#
- cvtsi2sd\\t{%1, %0|%0, %1}"
+ cvtsi2sd\t{%1, %0|%0, %1}"
[(set_attr "type" "fmov,multi,sse")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
[(set (match_operand:DF 0 "register_operand" "=Y")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE2"
- "cvtsi2sd\\t{%1, %0|%0, %1}"
+ "cvtsi2sd\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
"TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
"@
- fild%z1\\t%1
+ fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "DF")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
"TARGET_80387 && TARGET_64BIT && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
"@
- fild%z1\\t%1
+ fild%z1\t%1
#
- cvtsi2sd{q}\\t{%1, %0|%0, %1}"
+ cvtsi2sd{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "fmov,multi,sse")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
[(set (match_operand:DF 0 "register_operand" "=Y")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE2"
- "cvtsi2sd{q}\\t{%1, %0|%0, %1}"
+ "cvtsi2sd{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
(float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
"TARGET_80387 && !TARGET_64BIT"
"@
- fild%z1\\t%1
+ fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "XF")
(float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
"TARGET_80387"
"@
- fild%z1\\t%1
+ fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "XF")
(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
"TARGET_80387 && !TARGET_64BIT"
"@
- fild%z1\\t%1
+ fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "XF")
(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
"TARGET_80387"
"@
- fild%z1\\t%1
+ fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "XF")
(float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
"TARGET_80387 && !TARGET_64BIT"
"@
- fild%z1\\t%1
+ fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "XF")
(float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
"TARGET_80387"
"@
- fild%z1\\t%1
+ fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "XF")
"reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))
&& FP_REG_P (operands[0])"
[(const_int 0)]
- "
{
operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
ix86_free_from_memory (GET_MODE (operands[1]));
DONE;
-}")
+})
\f
;; Add instructions
(match_operand:DI 2 "x86_64_general_operand" "re,rm")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (PLUS, DImode, operands)"
- "adc{q}\\t{%2, %0|%0, %2}"
+ "adc{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "pent_pair" "pu")
(set_attr "mode" "DI")
(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
(plus:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
- "add{q}\\t{%2, %0|%0, %2}"
+ "add{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "DI")])
(match_operand:SI 2 "general_operand" "ri,rm")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (PLUS, SImode, operands)"
- "adc{l}\\t{%2, %0|%0, %2}"
+ "adc{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "pent_pair" "pu")
(set_attr "mode" "SI")
(match_operand:SI 2 "general_operand" "rim"))))
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
- "adc{l}\\t{%2, %k0|%k0, %2}"
+ "adc{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "pent_pair" "pu")
(set_attr "mode" "SI")
(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
(plus:SI (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (PLUS, SImode, operands)"
- "add{l}\\t{%2, %0|%0, %2}"
+ "add{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
(plus:QI (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (PLUS, QImode, operands)"
- "add{b}\\t{%2, %0|%0, %2}"
+ "add{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "address_operand" "p"))]
"!TARGET_64BIT"
- "lea{l}\\t{%a1, %0|%0, %a1}"
+ "lea{l}\t{%a1, %0|%0, %a1}"
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
[(set (match_operand:SI 0 "register_operand" "=r")
(subreg:SI (match_operand:DI 1 "address_operand" "p") 0))]
"TARGET_64BIT"
- "lea{l}\\t{%a1, %0|%0, %a1}"
+ "lea{l}\t{%a1, %0|%0, %a1}"
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))]
"TARGET_64BIT"
- "lea{l}\\t{%a1, %k0|%k0, %a1}"
+ "lea{l}\t{%a1, %k0|%k0, %a1}"
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 1 "address_operand" "p"))]
"TARGET_64BIT"
- "lea{q}\\t{%a1, %0|%0, %a1}"
+ "lea{q}\t{%a1, %0|%0, %a1}"
[(set_attr "type" "lea")
(set_attr "mode" "DI")])
"#"
"&& reload_completed"
[(const_int 0)]
- "
{
rtx pat;
operands[0] = gen_lowpart (SImode, operands[0]);
pat = gen_rtx_SUBREG (SImode, pat, 0);
emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
DONE;
-}"
+}
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
(zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
(match_dup 2))
(match_dup 3)) 0)))]
- "
{
operands[1] = gen_lowpart (Pmode, operands[1]);
operands[2] = gen_lowpart (Pmode, operands[2]);
operands[3] = gen_lowpart (Pmode, operands[3]);
-}"
+}
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
"#"
"&& reload_completed"
[(const_int 0)]
- "
{
rtx pat;
operands[0] = gen_lowpart (SImode, operands[0]);
pat = gen_rtx_SUBREG (SImode, pat, 0);
emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
DONE;
-}"
+}
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
(zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
(match_dup 2))
(match_dup 3)) 0)))]
- "
{
operands[1] = gen_lowpart (Pmode, operands[1]);
operands[3] = gen_lowpart (Pmode, operands[3]);
-}"
+}
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
"#"
"&& reload_completed"
[(const_int 0)]
- "
{
rtx pat;
operands[0] = gen_lowpart (SImode, operands[0]);
pat = gen_rtx_SUBREG (SImode, pat, 0);
emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
DONE;
-}"
+}
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
(match_dup 2))
(match_dup 3))
(match_dup 4)) 0)))]
- "
{
operands[1] = gen_lowpart (Pmode, operands[1]);
operands[3] = gen_lowpart (Pmode, operands[3]);
operands[4] = gen_lowpart (Pmode, operands[4]);
-}"
+}
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
(match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_LEA:
operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
- return \"lea{q}\\t{%a2, %0|%0, %a2}\";
+ return "lea{q}\t{%a2, %0|%0, %a2}";
case TYPE_INCDEC:
if (! rtx_equal_p (operands[0], operands[1]))
abort ();
if (operands[2] == const1_rtx)
- return \"inc{q}\\t%0\";
+ return "inc{q}\t%0";
else if (operands[2] == constm1_rtx)
- return \"dec{q}\\t%0\";
+ return "dec{q}\t%0";
else
abort ();
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (GET_CODE (operands[2]) == CONST_INT
/* Avoid overflows. */
- && ((INTVAL (operands[2]) & ((1 << 31) - 1)))
+ && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{q}\\t{%2, %0|%0, %2}\";
+ return "sub{q}\t{%2, %0|%0, %2}";
}
- return \"add{q}\\t{%2, %0|%0, %2}\";
+ return "add{q}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(cond [(eq_attr "alternative" "2")
(const_string "lea")
/* Current assemblers are broken and do not allow @GOTOFF in
ought but a memory context. */
&& ! pic_symbolic_operand (operands[2], VOIDmode)"
- "*
{
switch (get_attr_type (insn))
{
if (! rtx_equal_p (operands[0], operands[1]))
abort ();
if (operands[2] == const1_rtx)
- return \"inc{q}\\t%0\";
+ return "inc{q}\t%0";
else if (operands[2] == constm1_rtx)
- return \"dec{q}\\t%0\";
+ return "dec{q}\t%0";
else
abort ();
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (GET_CODE (operands[2]) == CONST_INT
/* Avoid overflows. */
- && ((INTVAL (operands[2]) & ((1 << 31) - 1)))
+ && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{q}\\t{%2, %0|%0, %2}\";
+ return "sub{q}\t{%2, %0|%0, %2}";
}
- return \"add{q}\\t{%2, %0|%0, %2}\";
+ return "add{q}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:DI 2 "incdec_operand" "")
(const_string "incdec")
/* Current assemblers are broken and do not allow @GOTOFF in
ought but a memory context. */
&& ! pic_symbolic_operand (operands[2], VOIDmode)"
- "*
{
switch (get_attr_type (insn))
{
if (! rtx_equal_p (operands[0], operands[1]))
abort ();
if (operands[2] == const1_rtx)
- return \"inc{q}\\t%0\";
+ return "inc{q}\t%0";
else if (operands[2] == constm1_rtx)
- return \"dec{q}\\t%0\";
+ return "dec{q}\t%0";
else
abort ();
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (GET_CODE (operands[2]) == CONST_INT
/* Avoid overflows. */
- && ((INTVAL (operands[2]) & ((1 << 31) - 1)))
+ && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{q}\\t{%2, %0|%0, %2}\";
+ return "sub{q}\t{%2, %0|%0, %2}";
}
- return \"add{q}\\t{%2, %0|%0, %2}\";
+ return "add{q}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:DI 2 "incdec_operand" "")
(const_string "incdec")
(clobber (match_scratch:DI 0 "=rm"))]
"TARGET_64BIT
&& ix86_match_ccmode (insn, CCGCmode)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == constm1_rtx)
- return \"inc{q}\\t%0\";
+ return "inc{q}\t%0";
else if (operands[2] == const1_rtx)
- return \"dec{q}\\t%0\";
+ return "dec{q}\t%0";
else
abort();
|| (INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) != 128))
/* Avoid overflows. */
- && ((INTVAL (operands[2]) & ((1 << 31) - 1))))
- return \"sub{q}\\t{%2, %0|%0, %2}\";
+ && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
+ return "sub{q}\t{%2, %0|%0, %2}";
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"add{q}\\t{%2, %0|%0, %2}\";
+ return "add{q}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:DI 2 "incdec_operand" "")
(const_string "incdec")
/* Current assemblers are broken and do not allow @GOTOFF in
ought but a memory context. */
&& ! pic_symbolic_operand (operands[2], VOIDmode)"
- "*
{
switch (get_attr_type (insn))
{
if (! rtx_equal_p (operands[0], operands[1]))
abort ();
if (operands[2] == const1_rtx)
- return \"inc{q}\\t%0\";
+ return "inc{q}\t%0";
else if (operands[2] == constm1_rtx)
- return \"dec{q}\\t%0\";
+ return "dec{q}\t%0";
else
abort();
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (GET_CODE (operands[2]) == CONST_INT
/* Avoid overflows. */
- && ((INTVAL (operands[2]) & ((1 << 31) - 1)))
+ && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{q}\\t{%2, %0|%0, %2}\";
+ return "sub{q}\t{%2, %0|%0, %2}";
}
- return \"add{q}\\t{%2, %0|%0, %2}\";
+ return "add{q}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:DI 2 "incdec_operand" "")
(const_string "incdec")
(match_operand:SI 2 "general_operand" "rmni,rni,rni")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (PLUS, SImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_LEA:
operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
- return \"lea{l}\\t{%a2, %0|%0, %a2}\";
+ return "lea{l}\t{%a2, %0|%0, %a2}";
case TYPE_INCDEC:
if (! rtx_equal_p (operands[0], operands[1]))
abort ();
if (operands[2] == const1_rtx)
- return \"inc{l}\\t%0\";
+ return "inc{l}\t%0";
else if (operands[2] == constm1_rtx)
- return \"dec{l}\\t%0\";
+ return "dec{l}\t%0";
else
abort();
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{l}\\t{%2, %0|%0, %2}\";
+ return "sub{l}\t{%2, %0|%0, %2}";
}
- return \"add{l}\\t{%2, %0|%0, %2}\";
+ return "add{l}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(cond [(eq_attr "alternative" "2")
(const_string "lea")
"reload_completed
&& true_regnum (operands[0]) != true_regnum (operands[1])"
[(const_int 0)]
- "
{
rtx pat;
/* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
pat = gen_rtx_SUBREG (SImode, pat, 0);
emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
DONE;
-}")
+})
;; It may seem that nonimmediate operand is proper one for operand 1.
;; The addsi_1 pattern allows nonimmediate operand at that place and
(match_operand:SI 2 "general_operand" "rmni,rni"))))
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_LEA:
operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
- return \"lea{l}\\t{%a2, %k0|%k0, %a2}\";
+ return "lea{l}\t{%a2, %k0|%k0, %a2}";
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return \"inc{l}\\t%k0\";
+ return "inc{l}\t%k0";
else if (operands[2] == constm1_rtx)
- return \"dec{l}\\t%k0\";
+ return "dec{l}\t%k0";
else
abort();
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{l}\\t{%2, %k0|%k0, %2}\";
+ return "sub{l}\t{%2, %k0|%k0, %2}";
}
- return \"add{l}\\t{%2, %k0|%k0, %2}\";
+ return "add{l}\t{%2, %k0|%k0, %2}";
}
-}"
+}
[(set (attr "type")
(cond [(eq_attr "alternative" "1")
(const_string "lea")
&& true_regnum (operands[0]) != true_regnum (operands[1])"
[(set (match_dup 0)
(zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
- "
{
operands[1] = gen_lowpart (Pmode, operands[1]);
operands[2] = gen_lowpart (Pmode, operands[2]);
-}")
+})
(define_insn "*addsi_2"
[(set (reg 17)
/* Current assemblers are broken and do not allow @GOTOFF in
ought but a memory context. */
&& ! pic_symbolic_operand (operands[2], VOIDmode)"
- "*
{
switch (get_attr_type (insn))
{
if (! rtx_equal_p (operands[0], operands[1]))
abort ();
if (operands[2] == const1_rtx)
- return \"inc{l}\\t%0\";
+ return "inc{l}\t%0";
else if (operands[2] == constm1_rtx)
- return \"dec{l}\\t%0\";
+ return "dec{l}\t%0";
else
abort();
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{l}\\t{%2, %0|%0, %2}\";
+ return "sub{l}\t{%2, %0|%0, %2}";
}
- return \"add{l}\\t{%2, %0|%0, %2}\";
+ return "add{l}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:SI 2 "incdec_operand" "")
(const_string "incdec")
/* Current assemblers are broken and do not allow @GOTOFF in
ought but a memory context. */
&& ! pic_symbolic_operand (operands[2], VOIDmode)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return \"inc{l}\\t%k0\";
+ return "inc{l}\t%k0";
else if (operands[2] == constm1_rtx)
- return \"dec{l}\\t%k0\";
+ return "dec{l}\t%k0";
else
abort();
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{l}\\t{%2, %k0|%k0, %2}\";
+ return "sub{l}\t{%2, %k0|%k0, %2}";
}
- return \"add{l}\\t{%2, %k0|%k0, %2}\";
+ return "add{l}\t{%2, %k0|%k0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:SI 2 "incdec_operand" "")
(const_string "incdec")
/* Current assemblers are broken and do not allow @GOTOFF in
ought but a memory context. */
&& ! pic_symbolic_operand (operands[2], VOIDmode)"
- "*
{
switch (get_attr_type (insn))
{
if (! rtx_equal_p (operands[0], operands[1]))
abort ();
if (operands[2] == const1_rtx)
- return \"inc{l}\\t%0\";
+ return "inc{l}\t%0";
else if (operands[2] == constm1_rtx)
- return \"dec{l}\\t%0\";
+ return "dec{l}\t%0";
else
abort();
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{l}\\t{%2, %0|%0, %2}\";
+ return "sub{l}\t{%2, %0|%0, %2}";
}
- return \"add{l}\\t{%2, %0|%0, %2}\";
+ return "add{l}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:SI 2 "incdec_operand" "")
(const_string "incdec")
/* Current assemblers are broken and do not allow @GOTOFF in
ought but a memory context. */
&& ! pic_symbolic_operand (operands[2], VOIDmode)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return \"inc{l}\\t%k0\";
+ return "inc{l}\t%k0";
else if (operands[2] == constm1_rtx)
- return \"dec{l}\\t%k0\";
+ return "dec{l}\t%k0";
else
abort();
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{l}\\t{%2, %k0|%k0, %2}\";
+ return "sub{l}\t{%2, %k0|%k0, %2}";
}
- return \"add{l}\\t{%2, %k0|%k0, %2}\";
+ return "add{l}\t{%2, %k0|%k0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:SI 2 "incdec_operand" "")
(const_string "incdec")
(clobber (match_scratch:SI 0 "=rm"))]
"ix86_match_ccmode (insn, CCGCmode)
&& (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == constm1_rtx)
- return \"inc{l}\\t%0\";
+ return "inc{l}\t%0";
else if (operands[2] == const1_rtx)
- return \"dec{l}\\t%0\";
+ return "dec{l}\t%0";
else
abort();
if ((INTVAL (operands[2]) == -128
|| (INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) != 128)))
- return \"sub{l}\\t{%2, %0|%0, %2}\";
+ return "sub{l}\t{%2, %0|%0, %2}";
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"add{l}\\t{%2, %0|%0, %2}\";
+ return "add{l}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:SI 2 "incdec_operand" "")
(const_string "incdec")
/* Current assemblers are broken and do not allow @GOTOFF in
ought but a memory context. */
&& ! pic_symbolic_operand (operands[2], VOIDmode)"
- "*
{
switch (get_attr_type (insn))
{
if (! rtx_equal_p (operands[0], operands[1]))
abort ();
if (operands[2] == const1_rtx)
- return \"inc{l}\\t%0\";
+ return "inc{l}\t%0";
else if (operands[2] == constm1_rtx)
- return \"dec{l}\\t%0\";
+ return "dec{l}\t%0";
else
abort();
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{l}\\t{%2, %0|%0, %2}\";
+ return "sub{l}\t{%2, %0|%0, %2}";
}
- return \"add{l}\\t{%2, %0|%0, %2}\";
+ return "add{l}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:SI 2 "incdec_operand" "")
(const_string "incdec")
(clobber (reg:CC 17))]
"!TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (PLUS, HImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_LEA:
- return \"#\";
+ return "#";
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return \"inc{w}\\t%0\";
+ return "inc{w}\t%0";
else if (operands[2] == constm1_rtx
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 65535))
- return \"dec{w}\\t%0\";
+ return "dec{w}\t%0";
abort();
default:
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{w}\\t{%2, %0|%0, %2}\";
+ return "sub{w}\t{%2, %0|%0, %2}";
}
- return \"add{w}\\t{%2, %0|%0, %2}\";
+ return "add{w}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (eq_attr "alternative" "2")
(const_string "lea")
(clobber (reg:CC 17))]
"TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (PLUS, HImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return \"inc{w}\\t%0\";
+ return "inc{w}\t%0";
else if (operands[2] == constm1_rtx
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 65535))
- return \"dec{w}\\t%0\";
+ return "dec{w}\t%0";
abort();
default:
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{w}\\t{%2, %0|%0, %2}\";
+ return "sub{w}\t{%2, %0|%0, %2}";
}
- return \"add{w}\\t{%2, %0|%0, %2}\";
+ return "add{w}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:HI 2 "incdec_operand" "")
(const_string "incdec")
(plus:HI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (PLUS, HImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return \"inc{w}\\t%0\";
+ return "inc{w}\t%0";
else if (operands[2] == constm1_rtx
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 65535))
- return \"dec{w}\\t%0\";
+ return "dec{w}\t%0";
abort();
default:
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{w}\\t{%2, %0|%0, %2}\";
+ return "sub{w}\t{%2, %0|%0, %2}";
}
- return \"add{w}\\t{%2, %0|%0, %2}\";
+ return "add{w}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:HI 2 "incdec_operand" "")
(const_string "incdec")
(clobber (match_scratch:HI 0 "=r"))]
"ix86_match_ccmode (insn, CCZmode)
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return \"inc{w}\\t%0\";
+ return "inc{w}\t%0";
else if (operands[2] == constm1_rtx
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 65535))
- return \"dec{w}\\t%0\";
+ return "dec{w}\t%0";
abort();
default:
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{w}\\t{%2, %0|%0, %2}\";
+ return "sub{w}\t{%2, %0|%0, %2}";
}
- return \"add{w}\\t{%2, %0|%0, %2}\";
+ return "add{w}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:HI 2 "incdec_operand" "")
(const_string "incdec")
(clobber (match_scratch:HI 0 "=rm"))]
"ix86_match_ccmode (insn, CCGCmode)
&& (INTVAL (operands[2]) & 0xffff) != 0x8000"
- "*
{
switch (get_attr_type (insn))
{
if (operands[2] == constm1_rtx
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 65535))
- return \"inc{w}\\t%0\";
+ return "inc{w}\t%0";
else if (operands[2] == const1_rtx)
- return \"dec{w}\\t%0\";
+ return "dec{w}\t%0";
else
abort();
if ((INTVAL (operands[2]) == -128
|| (INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) != 128)))
- return \"sub{w}\\t{%2, %0|%0, %2}\";
+ return "sub{w}\t{%2, %0|%0, %2}";
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"add{w}\\t{%2, %0|%0, %2}\";
+ return "add{w}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:HI 2 "incdec_operand" "")
(const_string "incdec")
(clobber (match_scratch:HI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return \"inc{w}\\t%0\";
+ return "inc{w}\t%0";
else if (operands[2] == constm1_rtx
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 65535))
- return \"dec{w}\\t%0\";
+ return "dec{w}\t%0";
abort();
default:
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{w}\\t{%2, %0|%0, %2}\";
+ return "sub{w}\t{%2, %0|%0, %2}";
}
- return \"add{w}\\t{%2, %0|%0, %2}\";
+ return "add{w}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:HI 2 "incdec_operand" "")
(const_string "incdec")
(clobber (reg:CC 17))]
"!TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (PLUS, QImode, operands)"
- "*
{
int widen = (which_alternative == 2);
switch (get_attr_type (insn))
{
case TYPE_LEA:
- return \"#\";
+ return "#";
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return widen ? \"inc{l}\\t%k0\" : \"inc{b}\\t%0\";
+ return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
else if (operands[2] == constm1_rtx
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 255))
- return widen ? \"dec{l}\\t%k0\" : \"dec{b}\\t%0\";
+ return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
abort();
default:
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
if (widen)
- return \"sub{l}\\t{%2, %k0|%k0, %2}\";
+ return "sub{l}\t{%2, %k0|%k0, %2}";
else
- return \"sub{b}\\t{%2, %0|%0, %2}\";
+ return "sub{b}\t{%2, %0|%0, %2}";
}
if (widen)
- return \"add{l}\\t{%k2, %k0|%k0, %k2}\";
+ return "add{l}\t{%k2, %k0|%k0, %k2}";
else
- return \"add{b}\\t{%2, %0|%0, %2}\";
+ return "add{b}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (eq_attr "alternative" "3")
(const_string "lea")
(clobber (reg:CC 17))]
"TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (PLUS, QImode, operands)"
- "*
{
int widen = (which_alternative == 2);
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return widen ? \"inc{l}\\t%k0\" : \"inc{b}\\t%0\";
+ return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
else if (operands[2] == constm1_rtx
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 255))
- return widen ? \"dec{l}\\t%k0\" : \"dec{b}\\t%0\";
+ return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
abort();
default:
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
if (widen)
- return \"sub{l}\\t{%2, %k0|%k0, %2}\";
+ return "sub{l}\t{%2, %k0|%k0, %2}";
else
- return \"sub{b}\\t{%2, %0|%0, %2}\";
+ return "sub{b}\t{%2, %0|%0, %2}";
}
if (widen)
- return \"add{l}\\t{%k2, %k0|%k0, %k2}\";
+ return "add{l}\t{%k2, %k0|%k0, %k2}";
else
- return \"add{b}\\t{%2, %0|%0, %2}\";
+ return "add{b}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(plus:QI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (PLUS, QImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return \"inc{b}\\t%0\";
+ return "inc{b}\t%0";
else if (operands[2] == constm1_rtx
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 255))
- return \"dec{b}\\t%0\";
+ return "dec{b}\t%0";
abort();
default:
&& INTVAL (operands[2]) < 0)
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{b}\\t{%2, %0|%0, %2}\";
+ return "sub{b}\t{%2, %0|%0, %2}";
}
- return \"add{b}\\t{%2, %0|%0, %2}\";
+ return "add{b}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(clobber (match_scratch:QI 0 "=q"))]
"ix86_match_ccmode (insn, CCZmode)
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return \"inc{b}\\t%0\";
+ return "inc{b}\t%0";
else if (operands[2] == constm1_rtx
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 255))
- return \"dec{b}\\t%0\";
+ return "dec{b}\t%0";
abort();
default:
&& INTVAL (operands[2]) < 0)
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{b}\\t{%2, %0|%0, %2}\";
+ return "sub{b}\t{%2, %0|%0, %2}";
}
- return \"add{b}\\t{%2, %0|%0, %2}\";
+ return "add{b}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(clobber (match_scratch:QI 0 "=qm"))]
"ix86_match_ccmode (insn, CCGCmode)
&& (INTVAL (operands[2]) & 0xff) != 0x80"
- "*
{
switch (get_attr_type (insn))
{
if (operands[2] == constm1_rtx
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 255))
- return \"inc{b}\\t%0\";
+ return "inc{b}\t%0";
else if (operands[2] == const1_rtx)
- return \"dec{b}\\t%0\";
+ return "dec{b}\t%0";
else
abort();
if (INTVAL (operands[2]) < 0)
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"add{b}\\t{%2, %0|%0, %2}\";
+ return "add{b}\t{%2, %0|%0, %2}";
}
- return \"sub{b}\\t{%2, %0|%0, %2}\";
+ return "sub{b}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:HI 2 "incdec_operand" "")
(const_string "incdec")
(clobber (match_scratch:QI 0 "=q"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return \"inc{b}\\t%0\";
+ return "inc{b}\t%0";
else if (operands[2] == constm1_rtx
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 255))
- return \"dec{b}\\t%0\";
+ return "dec{b}\t%0";
abort();
default:
&& INTVAL (operands[2]) < 0)
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{b}\\t{%2, %0|%0, %2}\";
+ return "sub{b}\t{%2, %0|%0, %2}";
}
- return \"add{b}\\t{%2, %0|%0, %2}\";
+ return "add{b}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(match_operand:QI 2 "general_operand" "Qmn")))
(clobber (reg:CC 17))]
"!TARGET_64BIT"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return \"inc{b}\\t%h0\";
+ return "inc{b}\t%h0";
else if (operands[2] == constm1_rtx
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 255))
- return \"dec{b}\\t%h0\";
+ return "dec{b}\t%h0";
abort();
default:
- return \"add{b}\\t{%2, %h0|%h0, %2}\";
+ return "add{b}\t{%2, %h0|%h0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(match_operand:QI 2 "nonmemory_operand" "Qn")))
(clobber (reg:CC 17))]
"TARGET_64BIT"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return \"inc{b}\\t%h0\";
+ return "inc{b}\t%h0";
else if (operands[2] == constm1_rtx
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 255))
- return \"dec{b}\\t%h0\";
+ return "dec{b}\t%h0";
abort();
default:
- return \"add{b}\\t{%2, %h0|%h0, %2}\";
+ return "add{b}\t{%2, %h0|%h0, %2}";
}
-}"
+}
[(set (attr "type")
(if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_int 8))))
(clobber (reg:CC 17))]
""
- "add{b}\\t{%h2, %h0|%h0, %h2}"
+ "add{b}\t{%h2, %h0|%h0, %h2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
(match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (MINUS, DImode, operands)"
- "sbb{q}\\t{%2, %0|%0, %2}"
+ "sbb{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "pent_pair" "pu")
(set_attr "ppro_uops" "few")
(match_operand:DI 2 "x86_64_general_operand" "re,rm")))
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
- "sub{q}\\t{%2, %0|%0, %2}"
+ "sub{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "DI")])
(minus:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (MINUS, DImode, operands)"
- "sub{q}\\t{%2, %0|%0, %2}"
+ "sub{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "DI")])
(minus:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
&& ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{q}\\t{%2, %0|%0, %2}"
+ "sub{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "DI")])
(match_operand:SI 2 "general_operand" "ri,rm"))))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sbb{l}\\t{%2, %0|%0, %2}"
+ "sbb{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "pent_pair" "pu")
(set_attr "ppro_uops" "few")
(match_operand:SI 2 "general_operand" "ri,rm")))))
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sbb{l}\\t{%2, %k0|%k0, %2}"
+ "sbb{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "pent_pair" "pu")
(set_attr "ppro_uops" "few")
(match_operand:SI 2 "general_operand" "ri,rm")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{l}\\t{%2, %0|%0, %2}"
+ "sub{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(match_operand:SI 2 "general_operand" "rim"))))
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{l}\\t{%2, %k0|%k0, %2}"
+ "sub{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(minus:SI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{l}\\t{%2, %0|%0, %2}"
+ "sub{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{l}\\t{%2, %k0|%k0, %2}"
+ "sub{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(minus:SI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCmode)
&& ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{l}\\t{%2, %0|%0, %2}"
+ "sub{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
&& ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{q}\\t{%2, %0|%0, %2}"
+ "sub{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "DI")])
(match_operand:HI 2 "general_operand" "ri,rm")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (MINUS, HImode, operands)"
- "sub{w}\\t{%2, %0|%0, %2}"
+ "sub{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "HI")])
(minus:HI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (MINUS, HImode, operands)"
- "sub{w}\\t{%2, %0|%0, %2}"
+ "sub{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "HI")])
(minus:HI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCmode)
&& ix86_binary_operator_ok (MINUS, HImode, operands)"
- "sub{w}\\t{%2, %0|%0, %2}"
+ "sub{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "HI")])
(match_operand:QI 2 "general_operand" "qn,qmn")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (MINUS, QImode, operands)"
- "sub{b}\\t{%2, %0|%0, %2}"
+ "sub{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
(minus:HI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (MINUS, QImode, operands)"
- "sub{b}\\t{%2, %0|%0, %2}"
+ "sub{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
(minus:HI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCmode)
&& ix86_binary_operator_ok (MINUS, QImode, operands)"
- "sub{b}\\t{%2, %0|%0, %2}"
+ "sub{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
"(GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
&& TARGET_64BIT"
"@
- imul{q}\\t{%2, %1, %0|%0, %1, %2}
- imul{q}\\t{%2, %1, %0|%0, %1, %2}
- imul{q}\\t{%2, %0|%0, %2}"
+ imul{q}\t{%2, %1, %0|%0, %1, %2}
+ imul{q}\t{%2, %1, %0|%0, %1, %2}
+ imul{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "imul")
(set_attr "prefix_0f" "0,0,1")
(set_attr "mode" "DI")])
; The first is simply short-hand for the latter. But, some assemblers,
; like the SCO OSR5 COFF assembler, don't handle the first form.
"@
- imul{l}\\t{%2, %1, %0|%0, %1, %2}
- imul{l}\\t{%2, %1, %0|%0, %1, %2}
- imul{l}\\t{%2, %0|%0, %2}"
+ imul{l}\t{%2, %1, %0|%0, %1, %2}
+ imul{l}\t{%2, %1, %0|%0, %1, %2}
+ imul{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "imul")
(set_attr "prefix_0f" "0,0,1")
(set_attr "mode" "SI")])
; The first is simply short-hand for the latter. But, some assemblers,
; like the SCO OSR5 COFF assembler, don't handle the first form.
"@
- imul{l}\\t{%2, %1, %k0|%k0, %1, %2}
- imul{l}\\t{%2, %1, %k0|%k0, %1, %2}
- imul{l}\\t{%2, %k0|%k0, %2}"
+ imul{l}\t{%2, %1, %k0|%k0, %1, %2}
+ imul{l}\t{%2, %1, %k0|%k0, %1, %2}
+ imul{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "imul")
(set_attr "prefix_0f" "0,0,1")
(set_attr "mode" "SI")])
; %%% There was a note about "Assembler has weird restrictions",
; concerning alternative 1 when op1 == op0. True?
"@
- imul{w}\\t{%2, %1, %0|%0, %1, %2}
- imul{w}\\t{%2, %1, %0|%0, %1, %2}
- imul{w}\\t{%2, %0|%0, %2}"
+ imul{w}\t{%2, %1, %0|%0, %1, %2}
+ imul{w}\t{%2, %1, %0|%0, %1, %2}
+ imul{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "imul")
(set_attr "prefix_0f" "0,0,1")
(set_attr "mode" "HI")])
(match_operand:QI 2 "nonimmediate_operand" "qm")))
(clobber (reg:CC 17))]
"TARGET_QIMODE_MATH"
- "mul{b}\\t%2"
+ "mul{b}\t%2"
[(set_attr "type" "imul")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
(zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
(clobber (reg:CC 17))]
"TARGET_QIMODE_MATH"
- "mul{b}\\t%2"
+ "mul{b}\t%2"
[(set_attr "type" "imul")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
(sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
(clobber (reg:CC 17))]
"TARGET_QIMODE_MATH"
- "imul{b}\\t%2"
+ "imul{b}\t%2"
[(set_attr "type" "imul")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
(zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
(clobber (reg:CC 17))]
"TARGET_64BIT"
- "mul{q}\\t%2"
+ "mul{q}\t%2"
[(set_attr "type" "imul")
(set_attr "ppro_uops" "few")
(set_attr "length_immediate" "0")
(zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
(clobber (reg:CC 17))]
"!TARGET_64BIT"
- "mul{l}\\t%2"
+ "mul{l}\t%2"
[(set_attr "type" "imul")
(set_attr "ppro_uops" "few")
(set_attr "length_immediate" "0")
(sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
(clobber (reg:CC 17))]
"TARGET_64BIT"
- "imul{q}\\t%2"
+ "imul{q}\t%2"
[(set_attr "type" "imul")
(set_attr "length_immediate" "0")
(set_attr "mode" "DI")])
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
(clobber (reg:CC 17))]
"!TARGET_64BIT"
- "imul{l}\\t%2"
+ "imul{l}\t%2"
[(set_attr "type" "imul")
(set_attr "length_immediate" "0")
(set_attr "mode" "SI")])
(clobber (match_scratch:DI 3 "=a"))
(clobber (reg:CC 17))]
"TARGET_64BIT"
- "mul{q}\\t%2"
+ "mul{q}\t%2"
[(set_attr "type" "imul")
(set_attr "ppro_uops" "few")
(set_attr "length_immediate" "0")
(clobber (match_scratch:SI 3 "=a"))
(clobber (reg:CC 17))]
""
- "mul{l}\\t%2"
+ "mul{l}\t%2"
[(set_attr "type" "imul")
(set_attr "ppro_uops" "few")
(set_attr "length_immediate" "0")
(clobber (match_scratch:SI 3 "=a"))
(clobber (reg:CC 17))]
"TARGET_64BIT"
- "mul{l}\\t%2"
+ "mul{l}\t%2"
[(set_attr "type" "imul")
(set_attr "ppro_uops" "few")
(set_attr "length_immediate" "0")
(clobber (match_scratch:DI 3 "=a"))
(clobber (reg:CC 17))]
"TARGET_64BIT"
- "imul{q}\\t%2"
+ "imul{q}\t%2"
[(set_attr "type" "imul")
(set_attr "ppro_uops" "few")
(set_attr "mode" "DI")])
(clobber (match_scratch:SI 3 "=a"))
(clobber (reg:CC 17))]
""
- "imul{l}\\t%2"
+ "imul{l}\t%2"
[(set_attr "type" "imul")
(set_attr "ppro_uops" "few")
(set_attr "mode" "SI")])
(clobber (match_scratch:SI 3 "=a"))
(clobber (reg:CC 17))]
"TARGET_64BIT"
- "imul{l}\\t%2"
+ "imul{l}\t%2"
[(set_attr "type" "imul")
(set_attr "ppro_uops" "few")
(set_attr "mode" "SI")])
(match_operand:QI 2 "nonimmediate_operand" "qm")))
(clobber (reg:CC 17))]
"TARGET_QIMODE_MATH"
- "idiv{b}\\t%2"
+ "idiv{b}\t%2"
[(set_attr "type" "idiv")
(set_attr "mode" "QI")
(set_attr "ppro_uops" "few")])
(match_operand:QI 2 "nonimmediate_operand" "qm")))
(clobber (reg:CC 17))]
"TARGET_QIMODE_MATH"
- "div{b}\\t%2"
+ "div{b}\t%2"
[(set_attr "type" "idiv")
(set_attr "mode" "QI")
(set_attr "ppro_uops" "few")])
(use (match_operand:DI 4 "register_operand" "3"))
(clobber (reg:CC 17))]
"TARGET_64BIT"
- "idiv{q}\\t%2"
+ "idiv{q}\t%2"
[(set_attr "type" "idiv")
(set_attr "mode" "DI")
(set_attr "ppro_uops" "few")])
(mod:DI (reg:DI 0) (match_dup 2)))
(use (match_dup 3))
(clobber (reg:CC 17))])]
- "
{
/* Avoid use of cltd in favour of a mov+shift. */
if (!TARGET_USE_CLTD && !optimize_size)
abort();
operands[4] = operands[1];
}
-}")
+})
(define_expand "divmodsi4"
(use (match_operand:SI 4 "register_operand" "3"))
(clobber (reg:CC 17))]
""
- "idiv{l}\\t%2"
+ "idiv{l}\t%2"
[(set_attr "type" "idiv")
(set_attr "mode" "SI")
(set_attr "ppro_uops" "few")])
(mod:SI (reg:SI 0) (match_dup 2)))
(use (match_dup 3))
(clobber (reg:CC 17))])]
- "
{
/* Avoid use of cltd in favour of a mov+shift. */
if (!TARGET_USE_CLTD && !optimize_size)
abort();
operands[4] = operands[1];
}
-}")
+})
;; %%% Split me.
(define_insn "divmodhi4"
[(set (match_operand:HI 0 "register_operand" "=a")
(mod:HI (match_dup 1) (match_dup 2)))
(clobber (reg:CC 17))]
"TARGET_HIMODE_MATH"
- "cwtd\;idiv{w}\\t%2"
+ "cwtd\;idiv{w}\t%2"
[(set_attr "type" "multi")
(set_attr "length_immediate" "0")
(set_attr "mode" "SI")])
(umod:DI (match_dup 1) (match_dup 2)))
(clobber (reg:CC 17))]
"TARGET_64BIT"
- "xor{q}\\t%3, %3\;div{q}\\t%2"
+ "xor{q}\t%3, %3\;div{q}\t%2"
[(set_attr "type" "multi")
(set_attr "length_immediate" "0")
(set_attr "mode" "DI")])
(use (match_dup 3))
(clobber (reg:CC 17))]
"TARGET_64BIT"
- "div{q}\\t%2"
+ "div{q}\t%2"
[(set_attr "type" "idiv")
(set_attr "ppro_uops" "few")
(set_attr "mode" "DI")])
(umod:SI (match_dup 1) (match_dup 2)))
(clobber (reg:CC 17))]
""
- "xor{l}\\t%3, %3\;div{l}\\t%2"
+ "xor{l}\t%3, %3\;div{l}\t%2"
[(set_attr "type" "multi")
(set_attr "length_immediate" "0")
(set_attr "mode" "SI")])
(use (match_dup 3))
(clobber (reg:CC 17))]
""
- "div{l}\\t%2"
+ "div{l}\t%2"
[(set_attr "type" "idiv")
(set_attr "ppro_uops" "few")
(set_attr "mode" "SI")])
(use (match_operand:HI 4 "register_operand" "3"))
(clobber (reg:CC 17))]
""
- "div{w}\\t%2"
+ "div{w}\t%2"
[(set_attr "type" "idiv")
(set_attr "mode" "HI")
(set_attr "ppro_uops" "few")])
; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
; (clobber (reg:CC 17))]
; ""
-; "div{l}\\t{%2, %0|%0, %2}"
+; "div{l}\t{%2, %0|%0, %2}"
; [(set_attr "type" "idiv")
; (set_attr "ppro_uops" "few")])
\f
(const_int 0)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"@
- test{l}\\t{%k1, %k0|%k0, %k1}
- test{l}\\t{%k1, %k0|%k0, %k1}
- test{q}\\t{%1, %0|%0, %1}
- test{q}\\t{%1, %0|%0, %1}
- test{q}\\t{%1, %0|%0, %1}"
+ test{l}\t{%k1, %k0|%k0, %k1}
+ test{l}\t{%k1, %k0|%k0, %k1}
+ test{q}\t{%1, %0|%0, %1}
+ test{q}\t{%1, %0|%0, %1}
+ test{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "test")
(set_attr "modrm" "0,1,0,1,1")
(set_attr "mode" "SI,SI,DI,DI,DI")
(match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
(const_int 0)))]
"ix86_match_ccmode (insn, CCNOmode)"
- "test{l}\\t{%1, %0|%0, %1}"
+ "test{l}\t{%1, %0|%0, %1}"
[(set_attr "type" "test")
(set_attr "modrm" "0,1,1")
(set_attr "mode" "SI")
(match_operand:HI 1 "nonmemory_operand" "n,n,rn"))
(const_int 0)))]
"ix86_match_ccmode (insn, CCNOmode)"
- "test{w}\\t{%1, %0|%0, %1}"
+ "test{w}\t{%1, %0|%0, %1}"
[(set_attr "type" "test")
(set_attr "modrm" "0,1,1")
(set_attr "mode" "HI")
(match_operand:QI 1 "nonmemory_operand" "n,n,qn,n"))
(const_int 0)))]
"ix86_match_ccmode (insn, CCNOmode)"
- "*
{
if (which_alternative == 3)
{
if (GET_CODE (operands[1]) == CONST_INT
&& (INTVAL (operands[1]) & 0xffffff00))
operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
- return \"test{l}\\t{%1, %k0|%k0, %1}\";
+ return "test{l}\t{%1, %k0|%k0, %1}";
}
- return \"test{b}\\t{%1, %0|%0, %1}\";
-}"
+ return "test{b}\t{%1, %0|%0, %1}";
+}
[(set_attr "type" "test")
(set_attr "modrm" "0,1,1,1")
(set_attr "mode" "QI,QI,QI,SI")
(const_int 0)))]
"(unsigned HOST_WIDE_INT) INTVAL (operands[1]) <= 0xff
&& ix86_match_ccmode (insn, CCNOmode)"
- "test{b}\\t{%1, %h0|%h0, %1}"
+ "test{b}\t{%1, %h0|%h0, %1}"
[(set_attr "type" "test")
(set_attr "mode" "QI")
(set_attr "length_immediate" "1")
(match_operand:QI 1 "nonimmediate_operand" "Qm")))
(const_int 0)))]
"!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
- "test{b}\\t{%1, %h0|%h0, %1}"
+ "test{b}\t{%1, %h0|%h0, %1}"
[(set_attr "type" "test")
(set_attr "mode" "QI")])
(match_operand:QI 1 "register_operand" "Q")))
(const_int 0)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
- "test{b}\\t{%1, %h0|%h0, %1}"
+ "test{b}\t{%1, %h0|%h0, %1}"
[(set_attr "type" "test")
(set_attr "mode" "QI")])
(const_int 8)))
(const_int 0)))]
"ix86_match_ccmode (insn, CCNOmode)"
- "test{b}\\t{%h1, %h0|%h0, %h1}"
+ "test{b}\t{%h1, %h0|%h0, %h1}"
[(set_attr "type" "test")
(set_attr "mode" "QI")])
(const_int 0)))]
"ix86_match_ccmode (insn, CCNOmode)"
[(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
- "
{
HOST_WIDE_INT len = INTVAL (operands[1]);
HOST_WIDE_INT pos = INTVAL (operands[2]);
operands[3] = gen_rtx_AND (mode, operands[0],
GEN_INT (trunc_int_for_mode (mask, mode)));
-}")
+})
;; %%% This used to optimize known byte-wide and operations to memory,
;; and sometimes to QImode registers. If this is considered useful,
(match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
operands[1] = gen_lowpart (mode, operands[1]);
if (mode == QImode)
- return \"movz{bq|x}\\t{%1,%0|%0, %1}\";
+ return "movz{bq|x}\t{%1,%0|%0, %1}";
else
- return \"movz{wq|x}\\t{%1,%0|%0, %1}\";
+ return "movz{wq|x}\t{%1,%0|%0, %1}";
}
default:
if (! rtx_equal_p (operands[0], operands[1]))
abort ();
if (get_attr_mode (insn) == MODE_SI)
- return \"and{l}\\t{%k2, %k0|%k0, %k2}\";
+ return "and{l}\t{%k2, %k0|%k0, %k2}";
else
- return \"and{q}\\t{%2, %0|%0, %2}\";
+ return "and{q}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set_attr "type" "alu,alu,alu,imovx")
(set_attr "length_immediate" "*,*,*,0")
(set_attr "mode" "SI,DI,DI,DI")])
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (AND, DImode, operands)"
"@
- and{l}\\t{%k2, %k0|%k0, %k2}
- and{q}\\t{%2, %0|%0, %2}
- and{q}\\t{%2, %0|%0, %2}"
+ and{l}\t{%k2, %k0|%k0, %k2}
+ and{q}\t{%2, %0|%0, %2}
+ and{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI,DI,DI")])
(match_operand:SI 2 "general_operand" "ri,rm,L")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (AND, SImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
operands[1] = gen_lowpart (mode, operands[1]);
if (mode == QImode)
- return \"movz{bl|x}\\t{%1,%0|%0, %1}\";
+ return "movz{bl|x}\t{%1,%0|%0, %1}";
else
- return \"movz{wl|x}\\t{%1,%0|%0, %1}\";
+ return "movz{wl|x}\t{%1,%0|%0, %1}";
}
default:
if (! rtx_equal_p (operands[0], operands[1]))
abort ();
- return \"and{l}\\t{%2, %0|%0, %2}\";
+ return "and{l}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set_attr "type" "alu,alu,imovx")
(set_attr "length_immediate" "*,*,0")
(set_attr "mode" "SI")])
(match_operand:SI 2 "general_operand" "rim"))))
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
- "and{l}\\t{%2, %k0|%k0, %2}"
+ "and{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(and:SI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (AND, SImode, operands)"
- "and{l}\\t{%2, %0|%0, %2}"
+ "and{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (AND, SImode, operands)"
- "and{l}\\t{%2, %k0|%k0, %2}"
+ "and{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(match_operand:HI 2 "general_operand" "ri,rm,L")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (AND, HImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
if (GET_CODE (operands[2]) != CONST_INT)
abort ();
if (INTVAL (operands[2]) == 0xff)
- return \"movz{bl|x}\\t{%b1, %k0|%k0, %b1}\";
+ return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
abort ();
default:
if (! rtx_equal_p (operands[0], operands[1]))
abort ();
- return \"and{w}\\t{%2, %0|%0, %2}\";
+ return "and{w}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set_attr "type" "alu,alu,imovx")
(set_attr "length_immediate" "*,*,0")
(set_attr "mode" "HI,HI,SI")])
(and:HI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (AND, HImode, operands)"
- "and{w}\\t{%2, %0|%0, %2}"
+ "and{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "HI")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (AND, QImode, operands)"
"@
- and{b}\\t{%2, %0|%0, %2}
- and{b}\\t{%2, %0|%0, %2}
- and{l}\\t{%k2, %k0|%k0, %k2}"
+ and{b}\t{%2, %0|%0, %2}
+ and{b}\t{%2, %0|%0, %2}
+ and{l}\t{%k2, %k0|%k0, %k2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI,QI,SI")])
(match_operand:QI 1 "general_operand" "qi,qmi")))
(clobber (reg:CC 17))]
""
- "and{b}\\t{%1, %0|%0, %1}"
+ "and{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
(and:QI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (AND, QImode, operands)"
- "*
{
if (which_alternative == 2)
{
if (GET_CODE (operands[2]) == CONST_INT
&& (INTVAL (operands[2]) & 0xffffff00))
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
- return \"and{l}\\t{%2, %k0|%k0, %2}\";
+ return "and{l}\t{%2, %k0|%k0, %2}";
}
- return \"and{b}\\t{%2, %0|%0, %2}\";
-}"
+ return "and{b}\t{%2, %0|%0, %2}";
+}
[(set_attr "type" "alu")
(set_attr "mode" "QI,QI,SI")])
(set (strict_low_part (match_dup 0))
(and:QI (match_dup 0) (match_dup 1)))]
"ix86_match_ccmode (insn, CCNOmode)"
- "and{b}\\t{%1, %0|%0, %1}"
+ "and{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
(match_operand 2 "const_int_operand" "n")))
(clobber (reg:CC 17))]
"(unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
- "and{b}\\t{%2, %h0|%h0, %2}"
+ "and{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
(set_attr "mode" "QI")])
(match_dup 2)))]
"ix86_match_ccmode (insn, CCNOmode)
&& (unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
- "and{b}\\t{%2, %h0|%h0, %2}"
+ "and{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
(set_attr "mode" "QI")])
(match_operand:QI 2 "general_operand" "Qm"))))
(clobber (reg:CC 17))]
"!TARGET_64BIT"
- "and{b}\\t{%2, %h0|%h0, %2}"
+ "and{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
(match_operand 2 "ext_register_operand" "Q"))))
(clobber (reg:CC 17))]
"TARGET_64BIT"
- "and{b}\\t{%2, %h0|%h0, %2}"
+ "and{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
(const_int 8))))
(clobber (reg:CC 17))]
""
- "and{b}\\t{%h2, %h0|%h0, %h2}"
+ "and{b}\t{%h2, %h0|%h0, %h2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
(clobber (reg:CC 17))]
"TARGET_64BIT
&& ix86_binary_operator_ok (IOR, DImode, operands)"
- "or{q}\\t{%2, %0|%0, %2}"
+ "or{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "DI")])
"TARGET_64BIT
&& ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (IOR, DImode, operands)"
- "or{q}\\t{%2, %0|%0, %2}"
+ "or{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "DI")])
"TARGET_64BIT
&& ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (IOR, DImode, operands)"
- "or{q}\\t{%2, %0|%0, %2}"
+ "or{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "DI")])
(match_operand:SI 2 "general_operand" "ri,rmi")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (IOR, SImode, operands)"
- "or{l}\\t{%2, %0|%0, %2}"
+ "or{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(match_operand:SI 2 "general_operand" "rim"))))
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
- "or{l}\\t{%2, %k0|%k0, %2}"
+ "or{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
(clobber (reg:CC 17))]
"TARGET_64BIT"
- "or{l}\\t{%2, %k0|%k0, %2}"
+ "or{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(ior:SI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (IOR, SImode, operands)"
- "or{l}\\t{%2, %0|%0, %2}"
+ "or{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (IOR, SImode, operands)"
- "or{l}\\t{%2, %k0|%k0, %2}"
+ "or{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (IOR, SImode, operands)"
- "or{l}\\t{%2, %k0|%k0, %2}"
+ "or{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(clobber (match_scratch:SI 0 "=r"))]
"ix86_match_ccmode (insn, CCNOmode)
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "or{l}\\t{%2, %0|%0, %2}"
+ "or{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(match_operand:HI 2 "general_operand" "rmi,ri")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (IOR, HImode, operands)"
- "or{w}\\t{%2, %0|%0, %2}"
+ "or{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "HI")])
(ior:HI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (IOR, HImode, operands)"
- "or{w}\\t{%2, %0|%0, %2}"
+ "or{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "HI")])
(clobber (match_scratch:HI 0 "=r"))]
"ix86_match_ccmode (insn, CCNOmode)
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "or{w}\\t{%2, %0|%0, %2}"
+ "or{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "HI")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (IOR, QImode, operands)"
"@
- or{b}\\t{%2, %0|%0, %2}
- or{b}\\t{%2, %0|%0, %2}
- or{l}\\t{%k2, %k0|%k0, %k2}"
+ or{b}\t{%2, %0|%0, %2}
+ or{b}\t{%2, %0|%0, %2}
+ or{l}\t{%k2, %k0|%k0, %k2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI,QI,SI")])
(match_operand:QI 1 "general_operand" "qmi,qi")))
(clobber (reg:CC 17))]
""
- "or{b}\\t{%1, %0|%0, %1}"
+ "or{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
(ior:QI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (IOR, QImode, operands)"
- "or{b}\\t{%2, %0|%0, %2}"
+ "or{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
(set (strict_low_part (match_dup 0))
(ior:QI (match_dup 0) (match_dup 1)))]
"ix86_match_ccmode (insn, CCNOmode)"
- "or{b}\\t{%1, %0|%0, %1}"
+ "or{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
(clobber (match_scratch:QI 0 "=q"))]
"ix86_match_ccmode (insn, CCNOmode)
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "or{b}\\t{%2, %0|%0, %2}"
+ "or{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
"TARGET_64BIT
&& ix86_binary_operator_ok (XOR, DImode, operands)"
"@
- xor{q}\\t{%2, %0|%0, %2}
- xor{q}\\t{%2, %0|%0, %2}"
+ xor{q}\t{%2, %0|%0, %2}
+ xor{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "DI,DI")])
&& ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (XOR, DImode, operands)"
"@
- xor{q}\\t{%2, %0|%0, %2}
- xor{q}\\t{%2, %0|%0, %2}"
+ xor{q}\t{%2, %0|%0, %2}
+ xor{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "DI,DI")])
"TARGET_64BIT
&& ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (XOR, DImode, operands)"
- "xor{q}\\t{%2, %0|%0, %2}"
+ "xor{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "DI")])
(match_operand:SI 2 "general_operand" "ri,rm")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (XOR, SImode, operands)"
- "xor{l}\\t{%2, %0|%0, %2}"
+ "xor{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(match_operand:SI 2 "general_operand" "rim"))))
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
- "xor{l}\\t{%2, %k0|%k0, %2}"
+ "xor{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
- "xor{l}\\t{%2, %k0|%k0, %2}"
+ "xor{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(xor:SI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (XOR, SImode, operands)"
- "xor{l}\\t{%2, %0|%0, %2}"
+ "xor{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (XOR, SImode, operands)"
- "xor{l}\\t{%2, %k0|%k0, %2}"
+ "xor{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (XOR, SImode, operands)"
- "xor{l}\\t{%2, %k0|%k0, %2}"
+ "xor{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(clobber (match_scratch:SI 0 "=r"))]
"ix86_match_ccmode (insn, CCNOmode)
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "xor{l}\\t{%2, %0|%0, %2}"
+ "xor{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(match_operand:HI 2 "general_operand" "rmi,ri")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (XOR, HImode, operands)"
- "xor{w}\\t{%2, %0|%0, %2}"
+ "xor{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "HI")])
(xor:HI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (XOR, HImode, operands)"
- "xor{w}\\t{%2, %0|%0, %2}"
+ "xor{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "HI")])
(clobber (match_scratch:HI 0 "=r"))]
"ix86_match_ccmode (insn, CCNOmode)
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "xor{w}\\t{%2, %0|%0, %2}"
+ "xor{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "HI")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (XOR, QImode, operands)"
"@
- xor{b}\\t{%2, %0|%0, %2}
- xor{b}\\t{%2, %0|%0, %2}
- xor{l}\\t{%k2, %k0|%k0, %k2}"
+ xor{b}\t{%2, %0|%0, %2}
+ xor{b}\t{%2, %0|%0, %2}
+ xor{l}\t{%k2, %k0|%k0, %k2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI,QI,SI")])
(const_int 8))))
(clobber (reg:CC 17))]
""
- "xor{b}\\t{%h2, %h0|%h0, %h2}"
+ "xor{b}\t{%h2, %h0|%h0, %h2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
(xor:QI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (XOR, QImode, operands)"
- "xor{b}\\t{%2, %0|%0, %2}"
+ "xor{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
(clobber (match_scratch:QI 0 "=q"))]
"ix86_match_ccmode (insn, CCNOmode)
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "xor{b}\\t{%2, %0|%0, %2}"
+ "xor{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
(zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
(match_dup 2)))]
"!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
- "xor{b}\\t{%2, %h0|%h0, %2}"
+ "xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
(zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
(match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
- "xor{b}\\t{%2, %h0|%h0, %2}"
+ "xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
(neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
- "neg{q}\\t%0"
+ "neg{q}\t%0"
[(set_attr "type" "negnot")
(set_attr "mode" "DI")])
(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(neg:DI (match_dup 1)))]
"TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
- "neg{q}\\t%0"
+ "neg{q}\t%0"
[(set_attr "type" "negnot")
(set_attr "mode" "DI")])
(neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
(clobber (reg:CC 17))]
"ix86_unary_operator_ok (NEG, SImode, operands)"
- "neg{l}\\t%0"
+ "neg{l}\t%0"
[(set_attr "type" "negnot")
(set_attr "mode" "SI")])
(const_int 32)))
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
- "neg{l}\\t%k0"
+ "neg{l}\t%k0"
[(set_attr "type" "negnot")
(set_attr "mode" "SI")])
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(neg:SI (match_dup 1)))]
"ix86_unary_operator_ok (NEG, SImode, operands)"
- "neg{l}\\t%0"
+ "neg{l}\t%0"
[(set_attr "type" "negnot")
(set_attr "mode" "SI")])
(const_int 32)))
(const_int 32)))]
"TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
- "neg{l}\\t%k0"
+ "neg{l}\t%k0"
[(set_attr "type" "negnot")
(set_attr "mode" "SI")])
(neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
(clobber (reg:CC 17))]
"ix86_unary_operator_ok (NEG, HImode, operands)"
- "neg{w}\\t%0"
+ "neg{w}\t%0"
[(set_attr "type" "negnot")
(set_attr "mode" "HI")])
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(neg:HI (match_dup 1)))]
"ix86_unary_operator_ok (NEG, HImode, operands)"
- "neg{w}\\t%0"
+ "neg{w}\t%0"
[(set_attr "type" "negnot")
(set_attr "mode" "HI")])
(neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
(clobber (reg:CC 17))]
"ix86_unary_operator_ok (NEG, QImode, operands)"
- "neg{b}\\t%0"
+ "neg{b}\t%0"
[(set_attr "type" "negnot")
(set_attr "mode" "QI")])
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(neg:QI (match_dup 1)))]
"ix86_unary_operator_ok (NEG, QImode, operands)"
- "neg{b}\\t%0"
+ "neg{b}\t%0"
[(set_attr "type" "negnot")
(set_attr "mode" "QI")])
[(set (subreg:TI (match_dup 0) 0)
(xor:TI (subreg:TI (match_dup 1) 0)
(subreg:TI (match_dup 2) 0)))]
- "
{
if (operands_match_p (operands[0], operands[2]))
{
operands[1] = operands[2];
operands[2] = tmp;
}
-}")
+})
;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
"TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
[(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
- "
{
int size = GET_MODE_SIZE (GET_MODE (operands[1]));
operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
operands[0] = adj_offsettable_operand (operands[0], size - 1);
operands[1] = GEN_INT (trunc_int_for_mode (0x80, QImode));
-}")
+})
(define_expand "negdf2"
[(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
[(set (subreg:TI (match_dup 0) 0)
(xor:TI (subreg:TI (match_dup 1) 0)
(subreg:TI (match_dup 2) 0)))]
- "
{
if (operands_match_p (operands[0], operands[2]))
{
operands[1] = operands[2];
operands[2] = tmp;
}
-}")
+})
;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
;; because of secondary memory needed to reload from class FLOAT_INT_REGS
"TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
[(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
- "
{
int size = GET_MODE_SIZE (GET_MODE (operands[1]));
operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
operands[0] = adj_offsettable_operand (operands[0], size - 1);
operands[1] = GEN_INT (trunc_int_for_mode (~0x80, QImode));
-}")
+})
(define_expand "absdf2"
[(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
"TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
- "not{q}\\t%0"
+ "not{q}\t%0"
[(set_attr "type" "negnot")
(set_attr "mode" "DI")])
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
"ix86_unary_operator_ok (NOT, SImode, operands)"
- "not{l}\\t%0"
+ "not{l}\t%0"
[(set_attr "type" "negnot")
(set_attr "mode" "SI")])
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
"TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
- "not{l}\\t%k0"
+ "not{l}\t%k0"
[(set_attr "type" "negnot")
(set_attr "mode" "SI")])
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
"ix86_unary_operator_ok (NOT, HImode, operands)"
- "not{w}\\t%0"
+ "not{w}\t%0"
[(set_attr "type" "negnot")
(set_attr "mode" "HI")])
(not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
"ix86_unary_operator_ok (NOT, QImode, operands)"
"@
- not{b}\\t%0
- not{l}\\t%k0"
+ not{b}\t%0
+ not{l}\t%k0"
[(set_attr "type" "negnot")
(set_attr "mode" "QI,SI")])
(match_operand:QI 2 "nonmemory_operand" "")))
(clobber (reg:CC 17))])]
""
- "
{
if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
{
}
ix86_expand_binary_operator (ASHIFT, DImode, operands);
DONE;
-}")
+})
(define_insn "*ashldi3_1_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
(match_operand:QI 2 "nonmemory_operand" "cJ,M")))
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
abort ();
if (!rtx_equal_p (operands[0], operands[1]))
abort ();
- return \"add{q}\\t{%0, %0|%0, %0}\";
+ return "add{q}\t{%0, %0|%0, %0}";
case TYPE_LEA:
if (GET_CODE (operands[2]) != CONST_INT
abort ();
operands[1] = gen_rtx_MULT (DImode, operands[1],
GEN_INT (1 << INTVAL (operands[2])));
- return \"lea{q}\\t{%a1, %0|%0, %a1}\";
+ return "lea{q}\t{%a1, %0|%0, %a1}";
default:
if (REG_P (operands[2]))
- return \"sal{q}\\t{%b2, %0|%0, %b2}\";
+ return "sal{q}\t{%b2, %0|%0, %b2}";
else if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 1
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO))
- return \"sal{q}\\t%0\";
+ return "sal{q}\t%0";
else
- return \"sal{q}\\t{%2, %0|%0, %2}\";
+ return "sal{q}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(cond [(eq_attr "alternative" "1")
(const_string "lea")
(ashift:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, DImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_ALU:
if (operands[2] != const1_rtx)
abort ();
- return \"add{q}\\t{%0, %0|%0, %0}\";
+ return "add{q}\t{%0, %0|%0, %0}";
default:
if (REG_P (operands[2]))
- return \"sal{q}\\t{%b2, %0|%0, %b2}\";
+ return "sal{q}\t{%b2, %0|%0, %b2}";
else if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 1
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO))
- return \"sal{q}\\t%0\";
+ return "sal{q}\t%0";
else
- return \"sal{q}\\t{%2, %0|%0, %2}\";
+ return "sal{q}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
(const_int 0))
(clobber (reg:CC 17))]
""
"@
- shld{l}\\t{%2, %1, %0|%0, %1, %2}
- shld{l}\\t{%s2%1, %0|%0, %1, %2}"
+ shld{l}\t{%2, %1, %0|%0, %1, %2}
+ shld{l}\t{%s2%1, %0|%0, %1, %2}"
[(set_attr "type" "ishift")
(set_attr "prefix_0f" "1")
(set_attr "mode" "SI")
(use (match_operand:SI 1 "register_operand" ""))
(use (match_operand:QI 2 "register_operand" ""))]
""
- "
{
rtx label = gen_label_rtx ();
rtx tmp;
LABEL_NUSES (label) = 1;
DONE;
-}")
+})
(define_expand "ashlsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "cI,M")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ASHIFT, SImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
abort ();
if (!rtx_equal_p (operands[0], operands[1]))
abort ();
- return \"add{l}\\t{%0, %0|%0, %0}\";
+ return "add{l}\t{%0, %0|%0, %0}";
case TYPE_LEA:
- return \"#\";
+ return "#";
default:
if (REG_P (operands[2]))
- return \"sal{l}\\t{%b2, %0|%0, %b2}\";
+ return "sal{l}\t{%b2, %0|%0, %b2}";
else if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 1
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO))
- return \"sal{l}\\t%0\";
+ return "sal{l}\t%0";
else
- return \"sal{l}\\t{%2, %0|%0, %2}\";
+ return "sal{l}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(cond [(eq_attr "alternative" "1")
(const_string "lea")
"reload_completed
&& true_regnum (operands[0]) != true_regnum (operands[1])"
[(const_int 0)]
- "
{
rtx pat;
operands[0] = gen_lowpart (SImode, operands[0]);
pat = gen_rtx_SUBREG (SImode, pat, 0);
emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
DONE;
-}")
+})
(define_insn "*ashlsi3_1_zext"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(match_operand:QI 2 "nonmemory_operand" "cI,M"))))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ASHIFT, SImode, operands) && TARGET_64BIT"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_ALU:
if (operands[2] != const1_rtx)
abort ();
- return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
+ return "add{l}\t{%k0, %k0|%k0, %k0}";
case TYPE_LEA:
- return \"#\";
+ return "#";
default:
if (REG_P (operands[2]))
- return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
+ return "sal{l}\t{%b2, %k0|%k0, %b2}";
else if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 1
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO))
- return \"sal{l}\\t%k0\";
+ return "sal{l}\t%k0";
else
- return \"sal{l}\\t{%2, %k0|%k0, %2}\";
+ return "sal{l}\t{%2, %k0|%k0, %2}";
}
-}"
+}
[(set (attr "type")
(cond [(eq_attr "alternative" "1")
(const_string "lea")
"reload_completed
&& true_regnum (operands[0]) != true_regnum (operands[1])"
[(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))]
- "
{
operands[1] = gen_lowpart (Pmode, operands[1]);
operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
Pmode));
-}")
+})
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
(ashift:SI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, SImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_ALU:
if (operands[2] != const1_rtx)
abort ();
- return \"add{l}\\t{%0, %0|%0, %0}\";
+ return "add{l}\t{%0, %0|%0, %0}";
default:
if (REG_P (operands[2]))
- return \"sal{l}\\t{%b2, %0|%0, %b2}\";
+ return "sal{l}\t{%b2, %0|%0, %b2}";
else if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 1
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO))
- return \"sal{l}\\t%0\";
+ return "sal{l}\t%0";
else
- return \"sal{l}\\t{%2, %0|%0, %2}\";
+ return "sal{l}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
(const_int 0))
(zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, SImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_ALU:
if (operands[2] != const1_rtx)
abort ();
- return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
+ return "add{l}\t{%k0, %k0|%k0, %k0}";
default:
if (REG_P (operands[2]))
- return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
+ return "sal{l}\t{%b2, %k0|%k0, %b2}";
else if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 1
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO))
- return \"sal{l}\\t%k0\";
+ return "sal{l}\t%k0";
else
- return \"sal{l}\\t{%2, %k0|%k0, %2}\";
+ return "sal{l}\t{%2, %k0|%k0, %2}";
}
-}"
+}
[(set (attr "type")
(cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
(const_int 0))
(clobber (reg:CC 17))]
"!TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (ASHIFT, HImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_LEA:
- return \"#\";
+ return "#";
case TYPE_ALU:
if (operands[2] != const1_rtx)
abort ();
- return \"add{w}\\t{%0, %0|%0, %0}\";
+ return "add{w}\t{%0, %0|%0, %0}";
default:
if (REG_P (operands[2]))
- return \"sal{w}\\t{%b2, %0|%0, %b2}\";
+ return "sal{w}\t{%b2, %0|%0, %b2}";
else if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 1
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO))
- return \"sal{w}\\t%0\";
+ return "sal{w}\t%0";
else
- return \"sal{w}\\t{%2, %0|%0, %2}\";
+ return "sal{w}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(cond [(eq_attr "alternative" "1")
(const_string "lea")
(clobber (reg:CC 17))]
"TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (ASHIFT, HImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_ALU:
if (operands[2] != const1_rtx)
abort ();
- return \"add{w}\\t{%0, %0|%0, %0}\";
+ return "add{w}\t{%0, %0|%0, %0}";
default:
if (REG_P (operands[2]))
- return \"sal{w}\\t{%b2, %0|%0, %b2}\";
+ return "sal{w}\t{%b2, %0|%0, %b2}";
else if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 1
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO))
- return \"sal{w}\\t%0\";
+ return "sal{w}\t%0";
else
- return \"sal{w}\\t{%2, %0|%0, %2}\";
+ return "sal{w}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
(const_int 0))
(ashift:HI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, HImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_ALU:
if (operands[2] != const1_rtx)
abort ();
- return \"add{w}\\t{%0, %0|%0, %0}\";
+ return "add{w}\t{%0, %0|%0, %0}";
default:
if (REG_P (operands[2]))
- return \"sal{w}\\t{%b2, %0|%0, %b2}\";
+ return "sal{w}\t{%b2, %0|%0, %b2}";
else if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 1
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO))
- return \"sal{w}\\t%0\";
+ return "sal{w}\t%0";
else
- return \"sal{w}\\t{%2, %0|%0, %2}\";
+ return "sal{w}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
(const_int 0))
(clobber (reg:CC 17))]
"!TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (ASHIFT, QImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_LEA:
- return \"#\";
+ return "#";
case TYPE_ALU:
if (operands[2] != const1_rtx)
abort ();
if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
- return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
+ return "add{l}\t{%k0, %k0|%k0, %k0}";
else
- return \"add{b}\\t{%0, %0|%0, %0}\";
+ return "add{b}\t{%0, %0|%0, %0}";
default:
if (REG_P (operands[2]))
{
if (get_attr_mode (insn) == MODE_SI)
- return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
+ return "sal{l}\t{%b2, %k0|%k0, %b2}";
else
- return \"sal{b}\\t{%b2, %0|%0, %b2}\";
+ return "sal{b}\t{%b2, %0|%0, %b2}";
}
else if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 1
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO))
{
if (get_attr_mode (insn) == MODE_SI)
- return \"sal{l}\\t%0\";
+ return "sal{l}\t%0";
else
- return \"sal{b}\\t%0\";
+ return "sal{b}\t%0";
}
else
{
if (get_attr_mode (insn) == MODE_SI)
- return \"sal{l}\\t{%2, %k0|%k0, %2}\";
+ return "sal{l}\t{%2, %k0|%k0, %2}";
else
- return \"sal{b}\\t{%2, %0|%0, %2}\";
+ return "sal{b}\t{%2, %0|%0, %2}";
}
}
-}"
+}
[(set (attr "type")
(cond [(eq_attr "alternative" "2")
(const_string "lea")
(clobber (reg:CC 17))]
"TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (ASHIFT, QImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
if (operands[2] != const1_rtx)
abort ();
if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
- return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
+ return "add{l}\t{%k0, %k0|%k0, %k0}";
else
- return \"add{b}\\t{%0, %0|%0, %0}\";
+ return "add{b}\t{%0, %0|%0, %0}";
default:
if (REG_P (operands[2]))
{
if (get_attr_mode (insn) == MODE_SI)
- return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
+ return "sal{l}\t{%b2, %k0|%k0, %b2}";
else
- return \"sal{b}\\t{%b2, %0|%0, %b2}\";
+ return "sal{b}\t{%b2, %0|%0, %b2}";
}
else if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 1
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO))
{
if (get_attr_mode (insn) == MODE_SI)
- return \"sal{l}\\t%0\";
+ return "sal{l}\t%0";
else
- return \"sal{b}\\t%0\";
+ return "sal{b}\t%0";
}
else
{
if (get_attr_mode (insn) == MODE_SI)
- return \"sal{l}\\t{%2, %k0|%k0, %2}\";
+ return "sal{l}\t{%2, %k0|%k0, %2}";
else
- return \"sal{b}\\t{%2, %0|%0, %2}\";
+ return "sal{b}\t{%2, %0|%0, %2}";
}
}
-}"
+}
[(set (attr "type")
(cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
(const_int 0))
(ashift:QI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, QImode, operands)"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_ALU:
if (operands[2] != const1_rtx)
abort ();
- return \"add{b}\\t{%0, %0|%0, %0}\";
+ return "add{b}\t{%0, %0|%0, %0}";
default:
if (REG_P (operands[2]))
- return \"sal{b}\\t{%b2, %0|%0, %b2}\";
+ return "sal{b}\t{%b2, %0|%0, %b2}";
else if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 1
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO))
- return \"sal{b}\\t%0\";
+ return "sal{b}\t%0";
else
- return \"sal{b}\\t{%2, %0|%0, %2}\";
+ return "sal{b}\t{%2, %0|%0, %2}";
}
-}"
+}
[(set (attr "type")
(cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
(const_int 0))
(match_operand:QI 2 "nonmemory_operand" "")))
(clobber (reg:CC 17))])]
""
- "
{
if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
{
}
ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
DONE;
-}")
+})
(define_insn "ashrdi3_63_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
"@
{cqto|cqo}
- sar{q}\\t{%2, %0|%0, %2}"
+ sar{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "imovx,ishift")
(set_attr "prefix_0f" "0,*")
(set_attr "length_immediate" "0,*")
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "sar{q}\\t%0"
+ "sar{q}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand:DI 0 "register_operand" "")
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
"@
- sar{q}\\t{%2, %0|%0, %2}
- sar{q}\\t{%b2, %0|%0, %b2}"
+ sar{q}\t{%2, %0|%0, %2}
+ sar{q}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
- "sar{q}\\t%0"
+ "sar{q}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand:DI 0 "register_operand" "")
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
- "sar{q}\\t{%2, %0|%0, %2}"
+ "sar{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
(clobber (reg:CC 17))]
""
"@
- shrd{l}\\t{%2, %1, %0|%0, %1, %2}
- shrd{l}\\t{%s2%1, %0|%0, %1, %2}"
+ shrd{l}\t{%2, %1, %0|%0, %1, %2}
+ shrd{l}\t{%s2%1, %0|%0, %1, %2}"
[(set_attr "type" "ishift")
(set_attr "prefix_0f" "1")
(set_attr "pent_pair" "np")
(use (match_operand:SI 1 "register_operand" ""))
(use (match_operand:QI 2 "register_operand" ""))]
""
- "
{
rtx label = gen_label_rtx ();
rtx tmp;
LABEL_NUSES (label) = 1;
DONE;
-}")
+})
(define_insn "ashrsi3_31"
[(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"@
{cltd|cdq}
- sar{l}\\t{%2, %0|%0, %2}"
+ sar{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "imovx,ishift")
(set_attr "prefix_0f" "0,*")
(set_attr "length_immediate" "0,*")
&& TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"@
{cltd|cdq}
- sar{l}\\t{%2, %k0|%k0, %2}"
+ sar{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "imovx,ishift")
(set_attr "prefix_0f" "0,*")
(set_attr "length_immediate" "0,*")
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "sar{l}\\t%0"
+ "sar{l}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand:SI 0 "register_operand" "")
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "sar{l}\\t%k0"
+ "sar{l}\t%k0"
[(set_attr "type" "ishift")
(set_attr "length" "2")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"@
- sar{l}\\t{%2, %0|%0, %2}
- sar{l}\\t{%b2, %0|%0, %b2}"
+ sar{l}\t{%2, %0|%0, %2}
+ sar{l}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"@
- sar{l}\\t{%2, %k0|%k0, %2}
- sar{l}\\t{%b2, %k0|%k0, %b2}"
+ sar{l}\t{%2, %k0|%k0, %2}
+ sar{l}\t{%b2, %k0|%k0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
"ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "sar{l}\\t%0"
+ "sar{l}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand:SI 0 "register_operand" "")
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "sar{l}\\t%k0"
+ "sar{l}\t%k0"
[(set_attr "type" "ishift")
(set_attr "length" "2")])
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "sar{l}\\t{%2, %0|%0, %2}"
+ "sar{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
(zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "sar{l}\\t{%2, %k0|%k0, %2}"
+ "sar{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "sar{w}\\t%0"
+ "sar{w}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
"@
- sar{w}\\t{%2, %0|%0, %2}
- sar{w}\\t{%b2, %0|%0, %b2}"
+ sar{w}\t{%2, %0|%0, %2}
+ sar{w}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "HI")])
"ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)
&& ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
- "sar{w}\\t%0"
+ "sar{w}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(ashiftrt:HI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
- "sar{w}\\t{%2, %0|%0, %2}"
+ "sar{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "HI")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "sar{b}\\t%0"
+ "sar{b}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
"@
- sar{b}\\t{%2, %0|%0, %2}
- sar{b}\\t{%b2, %0|%0, %b2}"
+ sar{b}\t{%2, %0|%0, %2}
+ sar{b}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "QI")])
"ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
- "sar{b}\\t%0"
+ "sar{b}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(ashiftrt:QI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
- "sar{b}\\t{%2, %0|%0, %2}"
+ "sar{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "QI")])
\f
(match_operand:QI 2 "nonmemory_operand" "")))
(clobber (reg:CC 17))])]
""
- "
{
if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
{
}
ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
DONE;
-}")
+})
(define_insn "*lshrdi3_1_one_bit_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "shr{q}\\t%0"
+ "shr{q}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand:DI 0 "register_operand" "")
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"@
- shr{q}\\t{%2, %0|%0, %2}
- shr{q}\\t{%b2, %0|%0, %b2}"
+ shr{q}\t{%2, %0|%0, %2}
+ shr{q}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
- "shr{q}\\t%0"
+ "shr{q}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand:DI 0 "register_operand" "")
(lshiftrt:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
- "shr{q}\\t{%2, %0|%0, %2}"
+ "shr{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "shr{l}\\t%0"
+ "shr{l}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand:SI 0 "register_operand" "")
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "shr{l}\\t%k0"
+ "shr{l}\t%k0"
[(set_attr "type" "ishift")
(set_attr "length" "2")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"@
- shr{l}\\t{%2, %0|%0, %2}
- shr{l}\\t{%b2, %0|%0, %b2}"
+ shr{l}\t{%2, %0|%0, %2}
+ shr{l}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"@
- shr{l}\\t{%2, %k0|%k0, %2}
- shr{l}\\t{%b2, %k0|%k0, %b2}"
+ shr{l}\t{%2, %k0|%k0, %2}
+ shr{l}\t{%b2, %k0|%k0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
"ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
- "shr{l}\\t%0"
+ "shr{l}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand:SI 0 "register_operand" "")
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
- "shr{l}\\t%k0"
+ "shr{l}\t%k0"
[(set_attr "type" "ishift")
(set_attr "length" "2")])
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
- "shr{l}\\t{%2, %0|%0, %2}"
+ "shr{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
(lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
- "shr{l}\\t{%2, %k0|%k0, %2}"
+ "shr{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "shr{w}\\t%0"
+ "shr{w}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"@
- shr{w}\\t{%2, %0|%0, %2}
- shr{w}\\t{%b2, %0|%0, %b2}"
+ shr{w}\t{%2, %0|%0, %2}
+ shr{w}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "HI")])
"ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
- "shr{w}\\t%0"
+ "shr{w}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand:SI 0 "register_operand" "")
(lshiftrt:HI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
- "shr{w}\\t{%2, %0|%0, %2}"
+ "shr{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "HI")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "shr{b}\\t%0"
+ "shr{b}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
"@
- shr{b}\\t{%2, %0|%0, %2}
- shr{b}\\t{%b2, %0|%0, %b2}"
+ shr{b}\t{%2, %0|%0, %2}
+ shr{b}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "QI")])
"ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)
&& ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
- "shr{b}\\t%0"
+ "shr{b}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand:SI 0 "register_operand" "")
(lshiftrt:QI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
- "shr{b}\\t{%2, %0|%0, %2}"
+ "shr{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "QI")])
\f
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "rol{q}\\t%0"
+ "rol{q}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand:DI 0 "register_operand" "")
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
"@
- rol{q}\\t{%2, %0|%0, %2}
- rol{q}\\t{%b2, %0|%0, %b2}"
+ rol{q}\t{%2, %0|%0, %2}
+ rol{q}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ROTATE, SImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "rol{l}\\t%0"
+ "rol{l}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand:SI 0 "register_operand" "")
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "rol{l}\\t%k0"
+ "rol{l}\t%k0"
[(set_attr "type" "ishift")
(set_attr "length" "2")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ROTATE, SImode, operands)"
"@
- rol{l}\\t{%2, %0|%0, %2}
- rol{l}\\t{%b2, %0|%0, %b2}"
+ rol{l}\t{%2, %0|%0, %2}
+ rol{l}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
"@
- rol{l}\\t{%2, %k0|%k0, %2}
- rol{l}\\t{%b2, %k0|%k0, %b2}"
+ rol{l}\t{%2, %k0|%k0, %2}
+ rol{l}\t{%b2, %k0|%k0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ROTATE, HImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "rol{w}\\t%0"
+ "rol{w}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ROTATE, HImode, operands)"
"@
- rol{w}\\t{%2, %0|%0, %2}
- rol{w}\\t{%b2, %0|%0, %b2}"
+ rol{w}\t{%2, %0|%0, %2}
+ rol{w}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "HI")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ROTATE, QImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "rol{b}\\t%0"
+ "rol{b}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ROTATE, QImode, operands)"
"@
- rol{b}\\t{%2, %0|%0, %2}
- rol{b}\\t{%b2, %0|%0, %b2}"
+ rol{b}\t{%2, %0|%0, %2}
+ rol{b}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "QI")])
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "ror{q}\\t%0"
+ "ror{q}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand:DI 0 "register_operand" "")
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
"@
- ror{q}\\t{%2, %0|%0, %2}
- ror{q}\\t{%b2, %0|%0, %b2}"
+ ror{q}\t{%2, %0|%0, %2}
+ ror{q}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ROTATERT, SImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "ror{l}\\t%0"
+ "ror{l}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand:SI 0 "register_operand" "")
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "ror{l}\\t%k0"
+ "ror{l}\t%k0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand:SI 0 "register_operand" "")
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ROTATERT, SImode, operands)"
"@
- ror{l}\\t{%2, %0|%0, %2}
- ror{l}\\t{%b2, %0|%0, %b2}"
+ ror{l}\t{%2, %0|%0, %2}
+ ror{l}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
(clobber (reg:CC 17))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
"@
- ror{l}\\t{%2, %k0|%k0, %2}
- ror{l}\\t{%b2, %k0|%k0, %b2}"
+ ror{l}\t{%2, %k0|%k0, %2}
+ ror{l}\t{%b2, %k0|%k0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ROTATERT, HImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "ror{w}\\t%0"
+ "ror{w}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ROTATERT, HImode, operands)"
"@
- ror{w}\\t{%2, %0|%0, %2}
- ror{w}\\t{%b2, %0|%0, %b2}"
+ ror{w}\t{%2, %0|%0, %2}
+ ror{w}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "HI")])
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ROTATERT, QImode, operands)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
- "ror{b}\\t%0"
+ "ror{b}\t%0"
[(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ROTATERT, QImode, operands)"
"@
- ror{b}\\t{%2, %0|%0, %2}
- ror{b}\\t{%b2, %0|%0, %b2}"
+ ror{b}\t{%2, %0|%0, %2}
+ ror{b}\t{%b2, %0|%0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "QI")])
\f
(match_operand:SI 2 "immediate_operand" "")
(match_operand:SI 3 "immediate_operand" "")))]
""
- "
{
/* Handle extractions from %ah et al. */
if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
matches the predicate, so check it again here. */
if (! register_operand (operands[1], VOIDmode))
FAIL;
-}")
+})
(define_expand "extzv"
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 2 "immediate_operand" "")
(match_operand:SI 3 "immediate_operand" "")))]
""
- "
{
/* Handle extractions from %ah et al. */
if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
matches the predicate, so check it again here. */
if (! register_operand (operands[1], VOIDmode))
FAIL;
-}")
+})
(define_expand "insv"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
(match_operand:SI 2 "immediate_operand" ""))
(match_operand:SI 3 "register_operand" ""))]
""
- "
{
/* Handle extractions from %ah et al. */
if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
matches the predicate, so check it again here. */
if (! register_operand (operands[0], VOIDmode))
FAIL;
-}")
+})
;; %%% bts, btr, btc, bt.
\f
(match_operator:QI 1 "ix86_comparison_operator"
[(reg 17) (const_int 0)]))]
""
- "set%C1\\t%0"
+ "set%C1\t%0"
[(set_attr "type" "setcc")
(set_attr "mode" "QI")])
(match_operator:QI 1 "ix86_comparison_operator"
[(reg 17) (const_int 0)]))]
""
- "set%C1\\t%0"
+ "set%C1\t%0"
[(set_attr "type" "setcc")
(set_attr "mode" "QI")])
[(match_operand:SF 2 "register_operand" "0")
(match_operand:SF 3 "nonimmediate_operand" "xm")]))]
"TARGET_SSE && reload_completed"
- "cmp%D1ss\\t{%3, %0|%0, %3}"
+ "cmp%D1ss\t{%3, %0|%0, %3}"
[(set_attr "type" "sse")
(set_attr "mode" "SF")])
[(match_operand:DF 2 "register_operand" "0")
(match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
"TARGET_SSE2 && reload_completed"
- "cmp%D1sd\\t{%3, %0|%0, %3}"
+ "cmp%D1sd\t{%3, %0|%0, %3}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")])
\f
(label_ref (match_operand 0 "" ""))
(pc)))]
""
- "%+j%C1\\t%l0"
+ "%+j%C1\t%l0"
[(set_attr "type" "ibr")
(set (attr "prefix_0f")
(if_then_else (and (ge (minus (match_dup 0) (pc))
(pc)
(label_ref (match_operand 0 "" ""))))]
""
- "%+j%c1\\t%l0"
+ "%+j%c1\t%l0"
[(set_attr "type" "ibr")
(set (attr "prefix_0f")
(if_then_else (and (ge (minus (match_dup 0) (pc))
(clobber (reg:CCFP 17))]
"reload_completed"
[(const_int 0)]
- "
{
ix86_split_fp_branch (operands[0], operands[1], operands[2],
operands[3], operands[4], NULL_RTX);
DONE;
-}")
+})
(define_split
[(set (pc)
(if_then_else (match_dup 6)
(match_dup 3)
(match_dup 4)))]
- "
{
ix86_split_fp_branch (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]);
DONE;
-}")
+})
\f
;; Unconditional and other jump instructions
[(set (pc)
(label_ref (match_operand 0 "" "")))]
""
- "jmp\\t%l0"
+ "jmp\t%l0"
[(set_attr "type" "ibr")])
(define_insn "indirect_jump"
[(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
""
- "jmp\\t%A0"
+ "jmp\t%A0"
[(set_attr "type" "ibr")
(set_attr "length_immediate" "0")])
[(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
(use (label_ref (match_operand 1 "" "")))]
"! flag_pic"
- "jmp\\t%A0"
+ "jmp\t%A0"
[(set_attr "type" "ibr")
(set_attr "length_immediate" "0")])
(parallel [(set (pc) (match_dup 7))
(use (label_ref (match_dup 3)))])]
"flag_pic"
- "
{
operands[5] = gen_reg_rtx (SImode);
operands[6] = gen_reg_rtx (SImode);
operands[7] = gen_reg_rtx (SImode);
operands[8] = pic_offset_table_rtx;
current_function_uses_pic_offset_table = 1;
-}")
+})
(define_insn "*tablejump_pic"
[(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
(use (label_ref (match_operand 1 "" "")))]
""
- "jmp\\t%A0"
+ "jmp\t%A0"
[(set_attr "type" "ibr")
(set_attr "length_immediate" "0")])
\f
(clobber (match_scratch:SI 3 "=X,X,r"))
(clobber (reg:CC 17))]
"TARGET_USE_LOOP && !TARGET_64BIT"
- "*
{
if (which_alternative != 0)
- return \"#\";
+ return "#";
if (get_attr_length (insn) == 2)
- return \"%+loop\\t%l0\";
+ return "%+loop\t%l0";
else
- return \"dec{l}\\t%1\;%+jne\\t%l0\";
-}"
+ return "dec{l}\t%1\;%+jne\t%l0";
+}
[(set_attr "ppro_uops" "many")
(set (attr "type")
(if_then_else (and (eq_attr "alternative" "0")
(plus:SI (reg:SI 7)
(match_operand:SI 3 "" "")))])]
"!TARGET_64BIT"
- "
{
if (operands[3] == const0_rtx)
{
XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
if (TARGET_64BIT)
abort();
-}")
+})
(define_insn "*call_pop_0"
[(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
(set (reg:SI 7) (plus:SI (reg:SI 7)
(match_operand:SI 2 "immediate_operand" "")))]
"!TARGET_64BIT"
- "*
{
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%P0\";
+ return "jmp\t%P0";
else
- return \"call\\t%P0\";
-}"
+ return "call\t%P0";
+}
[(set_attr "type" "call")])
(define_insn "*call_pop_1"
(set (reg:SI 7) (plus:SI (reg:SI 7)
(match_operand:SI 2 "immediate_operand" "i")))]
"!TARGET_64BIT"
- "*
{
if (constant_call_address_operand (operands[0], Pmode))
{
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%P0\";
+ return "jmp\t%P0";
else
- return \"call\\t%P0\";
+ return "call\t%P0";
}
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%A0\";
+ return "jmp\t%A0";
else
- return \"call\\t%A0\";
-}"
+ return "call\t%A0";
+}
[(set_attr "type" "call")])
(define_expand "call"
(use (match_operand 2 "" ""))]
;; Operand 1 not used on the i386.
""
- "
{
rtx insn;
/* Static functions and indirect calls don't need
}
insn = emit_call_insn (gen_call_exp (operands[0], operands[1]));
DONE;
-}")
+})
(define_expand "call_exp"
[(call (match_operand:QI 0 "" "")
[(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
(match_operand 1 "" ""))]
""
- "*
{
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%P0\";
+ return "jmp\t%P0";
else
- return \"call\\t%P0\";
-}"
+ return "call\t%P0";
+}
[(set_attr "type" "call")])
(define_insn "*call_1"
[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
(match_operand 1 "" ""))]
"!TARGET_64BIT"
- "*
{
if (constant_call_address_operand (operands[0], QImode))
{
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%P0\";
+ return "jmp\t%P0";
else
- return \"call\\t%P0\";
+ return "call\t%P0";
}
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%A0\";
+ return "jmp\t%A0";
else
- return \"call\\t%A0\";
-}"
+ return "call\t%A0";
+}
[(set_attr "type" "call")])
(define_insn "*call_1_rex64"
[(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
(match_operand 1 "" ""))]
"TARGET_64BIT"
- "*
{
if (constant_call_address_operand (operands[0], QImode))
{
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%P0\";
+ return "jmp\t%P0";
else
- return \"call\\t%P0\";
+ return "call\t%P0";
}
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%A0\";
+ return "jmp\t%A0";
else
- return \"call\\t%A0\";
-}"
+ return "call\t%A0";
+}
[(set_attr "type" "call")])
;; Call subroutine, returning value in operand 0
(plus:SI (reg:SI 7)
(match_operand:SI 4 "" "")))])]
"!TARGET_64BIT"
- "
{
if (operands[4] == const0_rtx)
{
current_function_uses_pic_offset_table = 1;
if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
-}")
+})
(define_expand "call_value"
[(set (match_operand 0 "" "")
(use (match_operand:SI 3 "" ""))]
;; Operand 2 not used on the i386.
""
- "
{
rtx insn;
/* Static functions and indirect calls don't need
insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
operands[2]));
DONE;
-}")
+})
(define_expand "call_value_exp"
[(set (match_operand 0 "" "")
(match_operand 1 "" "")
(match_operand 2 "" "")])]
""
- "
{
int i;
emit_insn (gen_blockage ());
DONE;
-}")
+})
\f
;; Prologue and epilogue instructions
(define_expand "return"
[(return)]
"ix86_can_use_return_insn_p ()"
- "
{
if (current_function_pops_args)
{
emit_jump_insn (gen_return_pop_internal (popc));
DONE;
}
-}")
+})
(define_insn "return_internal"
[(return)]
[(return)
(use (match_operand:SI 0 "const_int_operand" ""))]
"reload_completed"
- "ret\\t%0"
+ "ret\t%0"
[(set_attr "length" "3")
(set_attr "length_immediate" "2")
(set_attr "modrm" "0")])
[(return)
(use (match_operand:SI 0 "register_operand" "r"))]
"reload_completed"
- "jmp\\t%A0"
+ "jmp\t%A0"
[(set_attr "type" "ibr")
(set_attr "length_immediate" "0")])
(minus:SI (pc) (match_operand 2 "" ""))))] 1))
(clobber (reg:CC 17))]
"!TARGET_64BIT"
- "*
{
if (GET_CODE (operands[2]) == LABEL_REF)
operands[2] = XEXP (operands[2], 0);
if (TARGET_DEEP_BRANCH_PREDICTION)
- return \"add{l}\\t{%1, %0|%0, %1}\";
+ return "add{l}\t{%1, %0|%0, %1}";
else
- return \"add{l}\\t{%1+[.-%X2], %0|%0, %a1+(.-%X2)}\";
-}"
+ return "add{l}\t{%1+[.-%X2], %0|%0, %a1+(.-%X2)}";
+}
[(set_attr "type" "alu")
; Since this insn may have two constant operands, we must set the
; length manually.
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))] 2))]
"!TARGET_64BIT"
- "*
{
if (GET_CODE (operands[1]) == LABEL_REF)
operands[1] = XEXP (operands[1], 0);
- output_asm_insn (\"call\\t%X1\", operands);
+ output_asm_insn ("call\t%X1", operands);
if (! TARGET_DEEP_BRANCH_PREDICTION)
{
- ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
+ ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
CODE_LABEL_NUMBER (operands[1]));
}
RET;
-}"
+}
[(set_attr "type" "multi")])
(define_expand "epilogue"
[(use (match_operand 0 "register_operand" ""))
(use (match_operand 1 "register_operand" ""))]
""
- "
{
rtx tmp, sa = operands[0], ra = operands[1];
emit_insn (gen_eh_return_1 (sa));
emit_barrier ();
DONE;
-}")
+})
(define_insn_and_split "eh_return_1"
[(unspec_volatile [(match_operand 0 "register_operand" "c")] 13)]
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(ffs:SI (match_operand:SI 1 "general_operand" "")))]
""
- "
{
rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode);
rtx in = operands[1];
emit_move_insn (operands[0], out);
}
DONE;
-}")
+})
(define_insn "ffssi_1"
[(set (reg:CCZ 17)
(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_dup 1)] 5))]
""
- "bsf{l}\\t{%1, %0|%0, %1}"
+ "bsf{l}\t{%1, %0|%0, %1}"
[(set_attr "prefix_0f" "1")
(set_attr "ppro_uops" "few")])
"TARGET_80387 && reload_completed
&& FLOAT_MODE_P (GET_MODE (operands[0]))"
[(const_int 0)]
- "
{
operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
operands[2])));
ix86_free_from_memory (GET_MODE (operands[1]));
DONE;
-}")
+})
(define_split
[(set (match_operand 0 "register_operand" "")
"TARGET_80387 && reload_completed
&& FLOAT_MODE_P (GET_MODE (operands[0]))"
[(const_int 0)]
- "
{
operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
operands[4])));
ix86_free_from_memory (GET_MODE (operands[2]));
DONE;
-}")
+})
\f
;; FPU special functions.
[(set (match_operand:SF 0 "register_operand" "")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
"(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE"
- "
{
if (!TARGET_SSE)
operands[1] = force_reg (SFmode, operands[1]);
-}")
+})
(define_insn "sqrtsf2_1"
[(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
&& (TARGET_SSE && TARGET_MIX_SSE_I387)"
"@
fsqrt
- sqrtss\\t{%1, %0|%0, %1}"
+ sqrtss\t{%1, %0|%0, %1}"
[(set_attr "type" "fpspc,sse")
(set_attr "mode" "SF,SF")
(set_attr "athlon_decode" "direct,*")])
[(set (match_operand:SF 0 "register_operand" "=x")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
- "sqrtss\\t{%1, %0|%0, %1}"
+ "sqrtss\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "mode" "SF")
(set_attr "athlon_decode" "*")])
[(set (match_operand:DF 0 "register_operand" "")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
"(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE2"
- "
{
if (!TARGET_SSE2)
operands[1] = force_reg (DFmode, operands[1]);
-}")
+})
(define_insn "sqrtdf2_1"
[(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
&& (TARGET_SSE2 && TARGET_MIX_SSE_I387)"
"@
fsqrt
- sqrtsd\\t{%1, %0|%0, %1}"
+ sqrtsd\t{%1, %0|%0, %1}"
[(set_attr "type" "fpspc,sse")
(set_attr "mode" "DF,DF")
(set_attr "athlon_decode" "direct,*")])
[(set (match_operand:DF 0 "register_operand" "=Y")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2 && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
- "sqrtsd\\t{%1, %0|%0, %1}"
+ "sqrtsd\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")
(set_attr "athlon_decode" "*")])
(use (match_operand:SI 2 "nonmemory_operand" ""))
(use (match_operand:SI 3 "const_int_operand" ""))]
""
- "
{
if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
DONE;
else
FAIL;
-}")
+})
(define_expand "movstrdi"
[(use (match_operand:BLK 0 "memory_operand" ""))
(use (match_operand:DI 2 "nonmemory_operand" ""))
(use (match_operand:DI 3 "const_int_operand" ""))]
"TARGET_64BIT"
- "
{
if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
DONE;
else
FAIL;
-}")
+})
;; Most CPUs don't like single string operations
;; Handle this case here to simplify previous expander.
(parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8)))
(clobber (reg:CC 17))])]
"TARGET_64BIT"
- "
{
if (TARGET_SINGLE_STRINGOP || optimize_size)
{
}
else
operands[2] = gen_reg_rtx (DImode);
-}")
+})
(define_expand "strmovsi"
(parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
(clobber (reg:CC 17))])]
""
- "
{
if (TARGET_64BIT)
{
}
else
operands[2] = gen_reg_rtx (SImode);
-}")
+})
(define_expand "strmovsi_rex64"
[(set (match_dup 2)
(parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4)))
(clobber (reg:CC 17))])]
"TARGET_64BIT"
- "
{
if (TARGET_SINGLE_STRINGOP || optimize_size)
{
}
else
operands[2] = gen_reg_rtx (SImode);
-}")
+})
(define_expand "strmovhi"
[(set (match_dup 2)
(parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
(clobber (reg:CC 17))])]
""
- "
{
if (TARGET_64BIT)
{
}
else
operands[2] = gen_reg_rtx (HImode);
-}")
+})
(define_expand "strmovhi_rex64"
[(set (match_dup 2)
(parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2)))
(clobber (reg:CC 17))])]
"TARGET_64BIT"
- "
{
if (TARGET_SINGLE_STRINGOP || optimize_size)
{
}
else
operands[2] = gen_reg_rtx (HImode);
-}")
+})
(define_expand "strmovqi"
[(set (match_dup 2)
(parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
(clobber (reg:CC 17))])]
""
- "
{
if (TARGET_64BIT)
{
}
else
operands[2] = gen_reg_rtx (QImode);
-}")
+})
(define_expand "strmovqi_rex64"
[(set (match_dup 2)
(parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
(clobber (reg:CC 17))])]
"!TARGET_64BIT"
- "
{
if (TARGET_SINGLE_STRINGOP || optimize_size)
{
}
else
operands[2] = gen_reg_rtx (QImode);
-}")
+})
(define_insn "strmovdi_rex_1"
[(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
(use (match_operand:SI 1 "nonmemory_operand" ""))
(use (match_operand 2 "const_int_operand" ""))]
""
- "
{
if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
DONE;
else
FAIL;
-}")
+})
(define_expand "clrstrdi"
[(use (match_operand:BLK 0 "memory_operand" ""))
(use (match_operand:DI 1 "nonmemory_operand" ""))
(use (match_operand 2 "const_int_operand" ""))]
"TARGET_64BIT"
- "
{
if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
DONE;
else
FAIL;
-}")
+})
;; Most CPUs don't like single string operations
;; Handle this case here to simplify previous expander.
(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
(clobber (reg:CC 17))])]
"TARGET_64BIT"
- "
{
if (TARGET_SINGLE_STRINGOP || optimize_size)
{
emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
DONE;
}
-}")
+})
(define_expand "strsetsi"
[(set (mem:SI (match_operand:SI 0 "register_operand" ""))
(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
(clobber (reg:CC 17))])]
""
- "
{
if (TARGET_64BIT)
{
emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
DONE;
}
-}")
+})
(define_expand "strsetsi_rex64"
[(set (mem:SI (match_operand:DI 0 "register_operand" ""))
(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
(clobber (reg:CC 17))])]
"TARGET_64BIT"
- "
{
if (TARGET_SINGLE_STRINGOP || optimize_size)
{
emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
DONE;
}
-}")
+})
(define_expand "strsethi"
[(set (mem:HI (match_operand:SI 0 "register_operand" ""))
(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
(clobber (reg:CC 17))])]
""
- "
{
if (TARGET_64BIT)
{
emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
DONE;
}
-}")
+})
(define_expand "strsethi_rex64"
[(set (mem:HI (match_operand:DI 0 "register_operand" ""))
(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
(clobber (reg:CC 17))])]
"TARGET_64BIT"
- "
{
if (TARGET_SINGLE_STRINGOP || optimize_size)
{
emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
DONE;
}
-}")
+})
(define_expand "strsetqi"
[(set (mem:QI (match_operand:SI 0 "register_operand" ""))
(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
(clobber (reg:CC 17))])]
""
- "
{
if (TARGET_64BIT)
{
emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
DONE;
}
-}")
+})
(define_expand "strsetqi_rex64"
[(set (mem:QI (match_operand:DI 0 "register_operand" ""))
(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
(clobber (reg:CC 17))])]
"TARGET_64BIT"
- "
{
if (TARGET_SINGLE_STRINGOP || optimize_size)
{
emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
DONE;
}
-}")
+})
(define_insn "strsetdi_rex_1"
[(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
(use (match_operand 3 "general_operand" ""))
(use (match_operand 4 "immediate_operand" ""))]
""
- "
{
rtx addr1, addr2, out, outlow, count, countreg, align;
emit_move_insn (operands[0], out);
DONE;
-}")
+})
;; Produce a tri-state integer (-1, 0, 1) from condition codes.
(match_operand:QI 2 "immediate_operand" "")
(match_operand 3 "immediate_operand" "")] 0))]
""
- "
{
if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
DONE;
else
FAIL;
-}")
+})
(define_expand "strlendi"
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:QI 2 "immediate_operand" "")
(match_operand 3 "immediate_operand" "")] 0))]
""
- "
{
if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
DONE;
else
FAIL;
-}")
+})
(define_insn "strlenqi_1"
[(set (match_operand:SI 0 "register_operand" "=&c")
(const_int 0)))
(clobber (reg:CC 17))]
"TARGET_64BIT"
- "sbb{q}\\t%0, %0"
+ "sbb{q}\t%0, %0"
; Since we don't have the proper number of operands for an alu insn,
; fill in all the blanks.
[(set_attr "type" "alu")
"TARGET_64BIT && TARGET_CMOVE
&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
"@
- cmov%C1\\t{%2, %0|%0, %2}
- cmov%c1\\t{%3, %0|%0, %3}"
+ cmov%C1\t{%2, %0|%0, %2}
+ cmov%c1\t{%3, %0|%0, %3}"
[(set_attr "type" "icmov")
(set_attr "mode" "DI")])
(const_int 0)))
(clobber (reg:CC 17))]
""
- "sbb{l}\\t%0, %0"
+ "sbb{l}\t%0, %0"
; Since we don't have the proper number of operands for an alu insn,
; fill in all the blanks.
[(set_attr "type" "alu")
"TARGET_CMOVE
&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
"@
- cmov%C1\\t{%2, %0|%0, %2}
- cmov%c1\\t{%3, %0|%0, %3}"
+ cmov%C1\t{%2, %0|%0, %2}
+ cmov%c1\t{%3, %0|%0, %3}"
[(set_attr "type" "icmov")
(set_attr "mode" "SI")])
"TARGET_CMOVE
&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
"@
- cmov%C1\\t{%2, %0|%0, %2}
- cmov%c1\\t{%3, %0|%0, %3}"
+ cmov%C1\t{%2, %0|%0, %2}
+ cmov%c1\t{%3, %0|%0, %3}"
[(set_attr "type" "icmov")
(set_attr "mode" "HI")])
"TARGET_CMOVE
&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
"@
- fcmov%F1\\t{%2, %0|%0, %2}
- fcmov%f1\\t{%3, %0|%0, %3}
- cmov%C1\\t{%2, %0|%0, %2}
- cmov%c1\\t{%3, %0|%0, %3}"
+ fcmov%F1\t{%2, %0|%0, %2}
+ fcmov%f1\t{%3, %0|%0, %3}
+ cmov%C1\t{%2, %0|%0, %2}
+ cmov%c1\t{%3, %0|%0, %3}"
[(set_attr "type" "fcmov,fcmov,icmov,icmov")
(set_attr "mode" "SF,SF,SI,SI")])
"TARGET_CMOVE && !TARGET_64BIT
&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
"@
- fcmov%F1\\t{%2, %0|%0, %2}
- fcmov%f1\\t{%3, %0|%0, %3}
+ fcmov%F1\t{%2, %0|%0, %2}
+ fcmov%f1\t{%3, %0|%0, %3}
#
#"
[(set_attr "type" "fcmov,fcmov,multi,multi")
"TARGET_CMOVE && TARGET_64BIT
&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
"@
- fcmov%F1\\t{%2, %0|%0, %2}
- fcmov%f1\\t{%3, %0|%0, %3}
- cmov%C1\\t{%2, %0|%0, %2}
- cmov%c1\\t{%3, %0|%0, %3}"
+ fcmov%F1\t{%2, %0|%0, %2}
+ fcmov%f1\t{%3, %0|%0, %3}
+ cmov%C1\t{%2, %0|%0, %2}
+ cmov%c1\t{%3, %0|%0, %3}"
[(set_attr "type" "fcmov,fcmov,icmov,icmov")
(set_attr "mode" "DF")])
(match_operand:XF 3 "register_operand" "0,f")))]
"TARGET_CMOVE && !TARGET_64BIT"
"@
- fcmov%F1\\t{%2, %0|%0, %2}
- fcmov%f1\\t{%3, %0|%0, %3}"
+ fcmov%F1\t{%2, %0|%0, %2}
+ fcmov%f1\t{%3, %0|%0, %3}"
[(set_attr "type" "fcmov")
(set_attr "mode" "XF")])
(match_operand:TF 3 "register_operand" "0,f")))]
"TARGET_CMOVE"
"@
- fcmov%F1\\t{%2, %0|%0, %2}
- fcmov%f1\\t{%3, %0|%0, %3}"
+ fcmov%F1\t{%2, %0|%0, %2}
+ fcmov%f1\t{%3, %0|%0, %3}"
[(set_attr "type" "fcmov")
(set_attr "mode" "XF")])
(match_dup 1)
(match_dup 2)))]
"TARGET_SSE && reload_completed"
- "minss\\t{%2, %0|%0, %2}"
+ "minss\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")
(set_attr "mode" "SF")])
(match_dup 1)
(match_dup 2)))]
"TARGET_SSE2 && reload_completed"
- "minsd\\t{%2, %0|%0, %2}"
+ "minsd\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")])
(match_dup 1)
(match_dup 2)))]
"TARGET_SSE && reload_completed"
- "maxss\\t{%2, %0|%0, %2}"
+ "maxss\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")
(set_attr "mode" "SF")])
(match_dup 1)
(match_dup 2)))]
"TARGET_SSE2 && reload_completed"
- "maxsd\\t{%2, %0|%0, %2}"
+ "maxsd\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")])
\f
(clobber (reg:CC 17))
(clobber (mem:BLK (scratch)))])]
""
- "
{
if (TARGET_64BIT)
{
(operands[0], operands[1], operands[2]));
DONE;
}
-}")
+})
(define_insn "*pro_epilogue_adjust_stack_1"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(clobber (reg:CC 17))
(clobber (mem:BLK (scratch)))]
"!TARGET_64BIT"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_IMOV:
- return \"mov{l}\\t{%1, %0|%0, %1}\";
+ return "mov{l}\t{%1, %0|%0, %1}";
case TYPE_ALU:
if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{l}\\t{%2, %0|%0, %2}\";
+ return "sub{l}\t{%2, %0|%0, %2}";
}
- return \"add{l}\\t{%2, %0|%0, %2}\";
+ return "add{l}\t{%2, %0|%0, %2}";
case TYPE_LEA:
operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
- return \"lea{l}\\t{%a2, %0|%0, %a2}\";
+ return "lea{l}\t{%a2, %0|%0, %a2}";
default:
abort ();
}
-}"
+}
[(set (attr "type")
(cond [(eq_attr "alternative" "0")
(const_string "alu")
(clobber (reg:CC 17))
(clobber (mem:BLK (scratch)))]
"TARGET_64BIT"
- "*
{
switch (get_attr_type (insn))
{
case TYPE_IMOV:
- return \"mov{q}\\t{%1, %0|%0, %1}\";
+ return "mov{q}\t{%1, %0|%0, %1}";
case TYPE_ALU:
if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return \"sub{q}\\t{%2, %0|%0, %2}\";
+ return "sub{q}\t{%2, %0|%0, %2}";
}
- return \"add{q}\\t{%2, %0|%0, %2}\";
+ return "add{q}\t{%2, %0|%0, %2}";
case TYPE_LEA:
operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
- return \"lea{q}\\t{%a2, %0|%0, %a2}\";
+ return "lea{q}\t{%a2, %0|%0, %a2}";
default:
abort ();
}
-}"
+}
[(set (attr "type")
(cond [(eq_attr "alternative" "0")
(const_string "alu")
"!SSE_REG_P (operands[0]) && reload_completed
&& VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
[(const_int 0)]
- "
{
ix86_compare_op0 = operands[5];
ix86_compare_op1 = operands[4];
VOIDmode, operands[5], operands[4]);
ix86_expand_fp_movcc (operands);
DONE;
-}")
+})
;; Split SSE based conditional move into seqence:
;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
(subreg:TI (match_dup 3) 0)))
(set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
(subreg:TI (match_dup 7) 0)))]
- "
{
PUT_MODE (operands[1], GET_MODE (operands[0]));
if (operands_match_p (operands[0], operands[4]))
operands[6] = operands[4], operands[7] = operands[2];
else
operands[6] = operands[2], operands[7] = operands[4];
-}")
+})
;; Special case of conditional move we can handle effectivly.
;; Do not brother with the integer/floating point case, since these are
[(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
(set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
(subreg:TI (match_dup 7) 0)))]
- "
{
PUT_MODE (operands[1], GET_MODE (operands[0]));
if (!sse_comparison_operator (operands[1], VOIDmode))
operands[7] = operands[2];
operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
}
-}")
+})
(define_expand "allocate_stack_worker"
[(match_operand:SI 0 "register_operand" "")]
"TARGET_STACK_PROBE"
- "
{
if (TARGET_64BIT)
emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
else
emit_insn (gen_allocate_stack_worker_1 (operands[0]));
DONE;
-}")
+})
(define_insn "allocate_stack_worker_1"
[(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
(clobber (match_dup 0))
(clobber (reg:CC 17))]
"TARGET_STACK_PROBE && !TARGET_64BIT"
- "call\\t__alloca"
+ "call\t__alloca"
[(set_attr "type" "multi")
(set_attr "length" "5")])
(clobber (match_dup 0))
(clobber (reg:CC 17))]
"TARGET_STACK_PROBE && TARGET_64BIT"
- "call\\t__alloca"
+ "call\t__alloca"
[(set_attr "type" "multi")
(set_attr "length" "5")])
(minus:SI (reg:SI 7) (match_dup 1)))
(clobber (reg:CC 17))])]
"TARGET_STACK_PROBE"
- "
{
#ifdef CHECK_STACK_LIMIT
if (GET_CODE (operands[1]) == CONST_INT
emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
DONE;
-}")
+})
(define_expand "builtin_setjmp_receiver"
[(label_ref (match_operand 0 "" ""))]
"flag_pic && !TARGET_64BIT"
- "
{
load_pic_register ();
DONE;
-}")
+})
\f
;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
(set (reg:SI 7) (plus:SI (reg:SI 7)
(match_operand:SI 3 "immediate_operand" "")))]
"!TARGET_64BIT"
- "*
{
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%P1\";
+ return "jmp\t%P1";
else
- return \"call\\t%P1\";
-}"
+ return "call\t%P1";
+}
[(set_attr "type" "callv")])
(define_insn "*call_value_pop_1"
(set (reg:SI 7) (plus:SI (reg:SI 7)
(match_operand:SI 3 "immediate_operand" "i")))]
"!TARGET_64BIT"
- "*
{
if (constant_call_address_operand (operands[1], QImode))
{
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%P1\";
+ return "jmp\t%P1";
else
- return \"call\\t%P1\";
+ return "call\t%P1";
}
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%A1\";
+ return "jmp\t%A1";
else
- return \"call\\t%A1\";
-}"
+ return "call\t%A1";
+}
[(set_attr "type" "callv")])
(define_insn "*call_value_0"
(call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
(match_operand:SI 2 "" "")))]
"!TARGET_64BIT"
- "*
{
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%P1\";
+ return "jmp\t%P1";
else
- return \"call\\t%P1\";
-}"
+ return "call\t%P1";
+}
[(set_attr "type" "callv")])
(define_insn "*call_value_0_rex64"
(call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
(match_operand:DI 2 "const_int_operand" "")))]
"TARGET_64BIT"
- "*
{
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%P1\";
+ return "jmp\t%P1";
else
- return \"call\\t%P1\";
-}"
+ return "call\t%P1";
+}
[(set_attr "type" "callv")])
(define_insn "*call_value_1"
(call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
(match_operand:SI 2 "" "")))]
"!TARGET_64BIT"
- "*
{
if (constant_call_address_operand (operands[1], QImode))
{
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%P1\";
+ return "jmp\t%P1";
else
- return \"call\\t%P1\";
+ return "call\t%P1";
}
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%*%1\";
+ return "jmp\t%*%1";
else
- return \"call\\t%*%1\";
-}"
+ return "call\t%*%1";
+}
[(set_attr "type" "callv")])
(define_insn "*call_value_1_rex64"
(call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
(match_operand:DI 2 "" "")))]
"TARGET_64BIT"
- "*
{
if (constant_call_address_operand (operands[1], QImode))
{
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%P1\";
+ return "jmp\t%P1";
else
- return \"call\\t%P1\";
+ return "call\t%P1";
}
if (SIBLING_CALL_P (insn))
- return \"jmp\\t%A1\";
+ return "jmp\t%A1";
else
- return \"call\\t%A1\";
-}"
+ return "call\t%A1";
+}
[(set_attr "type" "callv")])
\f
(define_insn "trap"
[(trap_if (const_int 1) (const_int 5))]
""
- "int\\t$5")
+ "int\t$5")
;;; ix86 doesn't have conditional trap instructions, but we fake them
;;; for the sake of bounds checking. By emitting bounds checks as
[(match_dup 2) (const_int 0)])
(match_operand 1 "const_int_operand" ""))]
""
- "
{
emit_insn (gen_rtx_TRAP_IF (VOIDmode,
ix86_expand_compare (GET_CODE (operands[0]),
NULL, NULL),
operands[1]));
DONE;
-}")
+})
-(define_insn ""
+(define_insn "*conditional_trap_1"
[(trap_if (match_operator 0 "comparison_operator"
[(reg 17) (const_int 0)])
(match_operand 1 "const_int_operand" ""))]
""
- "*
{
operands[2] = gen_label_rtx ();
- output_asm_insn (\"j%c0\\t%l2\; int\\t%1\", operands);
- ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
+ output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
+ ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
CODE_LABEL_NUMBER (operands[2]));
RET;
-}")
+})
;; Pentium III SIMD instructions.
(match_operand:V4SF 1 "general_operand" "xm,x"))]
"TARGET_SSE"
;; @@@ let's try to use movaps here.
- "movaps\\t{%1, %0|%0, %1}"
+ "movaps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "movv4si_internal"
(match_operand:V4SI 1 "general_operand" "xm,x"))]
"TARGET_SSE"
;; @@@ let's try to use movaps here.
- "movaps\\t{%1, %0|%0, %1}"
+ "movaps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "movv8qi_internal"
[(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
(match_operand:V8QI 1 "general_operand" "ym,y"))]
"TARGET_MMX"
- "movq\\t{%1, %0|%0, %1}"
+ "movq\t{%1, %0|%0, %1}"
[(set_attr "type" "mmx")])
(define_insn "movv4hi_internal"
[(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
(match_operand:V4HI 1 "general_operand" "ym,y"))]
"TARGET_MMX"
- "movq\\t{%1, %0|%0, %1}"
+ "movq\t{%1, %0|%0, %1}"
[(set_attr "type" "mmx")])
(define_insn "movv2si_internal"
[(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
(match_operand:V2SI 1 "general_operand" "ym,y"))]
"TARGET_MMX"
- "movq\\t{%1, %0|%0, %1}"
+ "movq\t{%1, %0|%0, %1}"
[(set_attr "type" "mmx")])
(define_expand "movti"
[(set (match_operand:TI 0 "general_operand" "")
(match_operand:TI 1 "general_operand" ""))]
"TARGET_SSE"
- "
{
/* For constants other than zero into memory. We do not know how the
instructions used to build constants modify the upper 64 bits
emit_move_insn (operands[0], temp);
DONE;
}
-}")
+})
(define_expand "movv4sf"
[(set (match_operand:V4SF 0 "general_operand" "")
(match_operand:V4SF 1 "general_operand" ""))]
"TARGET_SSE"
- "
{
/* For constants other than zero into memory. We do not know how the
instructions used to build constants modify the upper 64 bits
emit_move_insn (operands[0], temp);
DONE;
}
-}")
+})
(define_expand "movv4si"
[(set (match_operand:V4SI 0 "general_operand" "")
(match_operand:V4SI 1 "general_operand" ""))]
"TARGET_MMX"
- "
{
/* For constants other than zero into memory. We do not know how the
instructions used to build constants modify the upper 64 bits
emit_move_insn (operands[0], temp);
DONE;
}
-}")
+})
(define_expand "movv2si"
[(set (match_operand:V2SI 0 "general_operand" "")
(match_operand:V2SI 1 "general_operand" ""))]
"TARGET_MMX"
- "
{
/* For constants other than zero into memory. We do not know how the
instructions used to build constants modify the upper 64 bits
emit_move_insn (operands[0], temp);
DONE;
}
-}")
+})
(define_expand "movv4hi"
[(set (match_operand:V4HI 0 "general_operand" "")
(match_operand:V4HI 1 "general_operand" ""))]
"TARGET_MMX"
- "
{
/* For constants other than zero into memory. We do not know how the
instructions used to build constants modify the upper 64 bits
emit_move_insn (operands[0], temp);
DONE;
}
-}")
+})
(define_expand "movv8qi"
[(set (match_operand:V8QI 0 "general_operand" "")
(match_operand:V8QI 1 "general_operand" ""))]
"TARGET_MMX"
- "
{
/* For constants other than zero into memory. We do not know how the
instructions used to build constants modify the upper 64 bits
emit_move_insn (operands[0], temp);
DONE;
}
-}")
+})
(define_insn_and_split "*pushti"
[(set (match_operand:TI 0 "push_operand" "=<")
(match_operand:TI 1 "general_operand" "xm,x"))]
"TARGET_SSE"
"@
- movaps\\t{%1, %0|%0, %1}
- movaps\\t{%1, %0|%0, %1}"
+ movaps\t{%1, %0|%0, %1}
+ movaps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
;; These two patterns are useful for specifying exactly whether to use
(unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 38))]
"TARGET_SSE"
"@
- movaps\\t{%1, %0|%0, %1}
- movaps\\t{%1, %0|%0, %1}"
+ movaps\t{%1, %0|%0, %1}
+ movaps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "sse_movups"
(unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 39))]
"TARGET_SSE"
"@
- movups\\t{%1, %0|%0, %1}
- movups\\t{%1, %0|%0, %1}"
+ movups\t{%1, %0|%0, %1}
+ movups\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))]
"TARGET_SSE"
- "movmskps\\t{%1, %0|%0, %1}"
+ "movmskps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "mmx_pmovmskb"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))]
"TARGET_SSE"
- "pmovmskb\\t{%1, %0|%0, %1}"
+ "pmovmskb\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "mmx_maskmovq"
(match_operand:V8QI 2 "register_operand" "y")] 32))]
"TARGET_SSE"
;; @@@ check ordering of operands in intel/nonintel syntax
- "maskmovq\\t{%2, %1|%1, %2}"
+ "maskmovq\t{%2, %1|%1, %2}"
[(set_attr "type" "sse")])
(define_insn "sse_movntv4sf"
[(set (match_operand:V4SF 0 "memory_operand" "=m")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
"TARGET_SSE"
- "movntps\\t{%1, %0|%0, %1}"
+ "movntps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "sse_movntdi"
[(set (match_operand:DI 0 "memory_operand" "=m")
(unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))]
"TARGET_SSE"
- "movntq\\t{%1, %0|%0, %1}"
+ "movntq\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "sse_movhlps"
(const_int 1)]))
(const_int 3)))]
"TARGET_SSE"
- "movhlps\\t{%2, %0|%0, %2}"
+ "movhlps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "sse_movlhps"
(const_int 1)]))
(const_int 12)))]
"TARGET_SSE"
- "movlhps\\t{%2, %0|%0, %2}"
+ "movlhps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "sse_movhps"
(match_operand:V4SF 2 "nonimmediate_operand" "m,x")
(const_int 12)))]
"TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
- "movhps\\t{%2, %0|%0, %2}"
+ "movhps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "sse_movlps"
(match_operand:V4SF 2 "nonimmediate_operand" "m,x")
(const_int 3)))]
"TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
- "movlps\\t{%2, %0|%0, %2}"
+ "movlps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "sse_loadss"
(vec_duplicate:V4SF (float:SF (const_int 0)))
(const_int 1)))]
"TARGET_SSE"
- "movss\\t{%1, %0|%0, %1}"
+ "movss\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "sse_movss"
(match_operand:V4SF 2 "register_operand" "x")
(const_int 1)))]
"TARGET_SSE"
- "movss\\t{%2, %0|%0, %2}"
+ "movss\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "sse_storess"
(match_operand:V4SF 1 "register_operand" "x")
(parallel [(const_int 0)])))]
"TARGET_SSE"
- "movss\\t{%1, %0|%0, %1}"
+ "movss\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "sse_shufps"
(match_operand:SI 3 "immediate_operand" "i")] 41))]
"TARGET_SSE"
;; @@@ check operand order for intel/nonintel syntax
- "shufps\\t{%3, %2, %0|%0, %2, %3}"
+ "shufps\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse")])
(plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
- "addps\\t{%2, %0|%0, %2}"
+ "addps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "vmaddv4sf3"
(match_dup 1)
(const_int 1)))]
"TARGET_SSE"
- "addss\\t{%2, %0|%0, %2}"
+ "addss\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "subv4sf3"
(minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
- "subps\\t{%2, %0|%0, %2}"
+ "subps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "vmsubv4sf3"
(match_dup 1)
(const_int 1)))]
"TARGET_SSE"
- "subss\\t{%2, %0|%0, %2}"
+ "subss\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "mulv4sf3"
(mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
- "mulps\\t{%2, %0|%0, %2}"
+ "mulps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "vmmulv4sf3"
(match_dup 1)
(const_int 1)))]
"TARGET_SSE"
- "mulss\\t{%2, %0|%0, %2}"
+ "mulss\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "divv4sf3"
(div:V4SF (match_operand:V4SF 1 "register_operand" "0")
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
- "divps\\t{%2, %0|%0, %2}"
+ "divps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "vmdivv4sf3"
(match_dup 1)
(const_int 1)))]
"TARGET_SSE"
- "divss\\t{%2, %0|%0, %2}"
+ "divss\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
[(set (match_operand:V4SF 0 "register_operand" "=x")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42))]
"TARGET_SSE"
- "rcpps\\t{%1, %0|%0, %1}"
+ "rcpps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "vmrcpv4sf2"
(match_operand:V4SF 2 "register_operand" "0")
(const_int 1)))]
"TARGET_SSE"
- "rcpss\\t{%1, %0|%0, %1}"
+ "rcpss\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "rsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43))]
"TARGET_SSE"
- "rsqrtps\\t{%1, %0|%0, %1}"
+ "rsqrtps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "vmrsqrtv4sf2"
(match_operand:V4SF 2 "register_operand" "0")
(const_int 1)))]
"TARGET_SSE"
- "rsqrtss\\t{%1, %0|%0, %1}"
+ "rsqrtss\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "sqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm")))]
"TARGET_SSE"
- "sqrtps\\t{%1, %0|%0, %1}"
+ "sqrtps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "vmsqrtv4sf2"
(match_operand:V4SF 2 "register_operand" "0")
(const_int 1)))]
"TARGET_SSE"
- "sqrtss\\t{%1, %0|%0, %1}"
+ "sqrtss\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
"TARGET_SSE2"
- "andpd\\t{%2, %0|%0, %2}"
+ "andpd\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_andti3_df_2"
(and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
- "andpd\\t{%2, %0|%0, %2}"
+ "andpd\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_andti3_sf_1"
(and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
"TARGET_SSE"
- "andps\\t{%2, %0|%0, %2}"
+ "andps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_andti3_sf_2"
(and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
- "andps\\t{%2, %0|%0, %2}"
+ "andps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "sse_andti3"
(and:TI (match_operand:TI 1 "register_operand" "%0")
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE && !TARGET_SSE2"
- "andps\\t{%2, %0|%0, %2}"
+ "andps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_andti3_sse2"
(and:TI (match_operand:TI 1 "register_operand" "%0")
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
- "pand\\t{%2, %0|%0, %2}"
+ "pand\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_nandti3_df"
(and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
- "andnpd\\t{%2, %0|%0, %2}"
+ "andnpd\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_nandti3_sf"
(and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0))
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
- "andnps\\t{%2, %0|%0, %2}"
+ "andnps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "sse_nandti3"
(and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE && !TARGET_SSE2"
- "andnps\\t{%2, %0|%0, %2}"
+ "andnps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_nandti3_sse2"
(and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
- "pnand\\t{%2, %0|%0, %2}"
+ "pnand\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_iorti3_df_1"
(ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
"TARGET_SSE2"
- "orpd\\t{%2, %0|%0, %2}"
+ "orpd\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_iorti3_df_2"
(ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
- "orpd\\t{%2, %0|%0, %2}"
+ "orpd\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_iorti3_sf_1"
(ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
"TARGET_SSE"
- "orps\\t{%2, %0|%0, %2}"
+ "orps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_iorti3_sf_2"
(ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
- "orps\\t{%2, %0|%0, %2}"
+ "orps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "sse_iorti3"
(ior:TI (match_operand:TI 1 "register_operand" "%0")
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE && !TARGET_SSE2"
- "orps\\t{%2, %0|%0, %2}"
+ "orps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_iorti3_sse2"
(ior:TI (match_operand:TI 1 "register_operand" "%0")
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
- "por\\t{%2, %0|%0, %2}"
+ "por\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_xorti3_df_1"
(xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
"TARGET_SSE2"
- "xorpd\\t{%2, %0|%0, %2}"
+ "xorpd\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_xorti3_df_2"
(xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
- "xorpd\\t{%2, %0|%0, %2}"
+ "xorpd\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_xorti3_sf_1"
(xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
"TARGET_SSE"
- "xorps\\t{%2, %0|%0, %2}"
+ "xorps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_xorti3_sf_2"
(xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
- "xorps\\t{%2, %0|%0, %2}"
+ "xorps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "sse_xorti3"
(xor:TI (match_operand:TI 1 "register_operand" "%0")
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE && !TARGET_SSE2"
- "xorps\\t{%2, %0|%0, %2}"
+ "xorps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "*sse_xorti3_sse2"
(xor:TI (match_operand:TI 1 "register_operand" "%0")
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
- "pxor\\t{%2, %0|%0, %2}"
+ "pxor\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
;; Use xor, but don't show input operands so they aren't live before
[(set (match_operand:TI 0 "register_operand" "=x")
(unspec:TI [(const_int 0)] 45))]
"TARGET_SSE"
- "xorps\\t{%0, %0|%0, %0}"
+ "xorps\t{%0, %0|%0, %0}"
[(set_attr "type" "sse")])
[(match_operand:V4SF 1 "register_operand" "0")
(match_operand:V4SF 2 "nonimmediate_operand" "x")]))]
"TARGET_SSE"
- "cmp%D3ps\\t{%2, %0|%0, %2}"
+ "cmp%D3ps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "maskncmpv4sf3"
[(match_operand:V4SF 1 "register_operand" "0")
(match_operand:V4SF 2 "nonimmediate_operand" "x")])))]
"TARGET_SSE"
- "cmpn%D3ps\\t{%2, %0|%0, %2}"
+ "cmpn%D3ps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "vmmaskcmpv4sf3"
(match_dup 1)
(const_int 1)))]
"TARGET_SSE"
- "cmp%D3ss\\t{%2, %0|%0, %2}"
+ "cmp%D3ss\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "vmmaskncmpv4sf3"
(subreg:V4SI (match_dup 1) 0)
(const_int 1)))]
"TARGET_SSE"
- "cmp%D3ss\\t{%2, %0|%0, %2}"
+ "cmp%D3ss\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "sse_comi"
(match_operand:V4SF 1 "register_operand" "x")
(parallel [(const_int 0)]))]))]
"TARGET_SSE"
- "comiss\\t{%2, %0|%0, %2}"
+ "comiss\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "sse_ucomi"
(match_operand:V4SF 1 "register_operand" "x")
(parallel [(const_int 0)]))]))]
"TARGET_SSE"
- "ucomiss\\t{%2, %0|%0, %2}"
+ "ucomiss\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(const_int 3)]))
(const_int 5)))]
"TARGET_SSE"
- "unpckhps\\t{%2, %0|%0, %2}"
+ "unpckhps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "sse_unpcklps"
(const_int 1)]))
(const_int 5)))]
"TARGET_SSE"
- "unpcklps\\t{%2, %0|%0, %2}"
+ "unpcklps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
- "maxps\\t{%2, %0|%0, %2}"
+ "maxps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "vmsmaxv4sf3"
(match_dup 1)
(const_int 1)))]
"TARGET_SSE"
- "maxss\\t{%2, %0|%0, %2}"
+ "maxss\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "sminv4sf3"
(smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
- "minps\\t{%2, %0|%0, %2}"
+ "minps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "vmsminv4sf3"
(match_dup 1)
(const_int 1)))]
"TARGET_SSE"
- "minss\\t{%2, %0|%0, %2}"
+ "minss\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(float:V2SF (match_operand:V2SI 2 "register_operand" "ym")))
(const_int 12)))]
"TARGET_SSE"
- "cvtpi2ps\\t{%2, %0|%0, %2}"
+ "cvtpi2ps\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "cvtps2pi"
[(const_int 0)
(const_int 1)])))]
"TARGET_SSE"
- "cvtps2pi\\t{%1, %0|%0, %1}"
+ "cvtps2pi\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "cvttps2pi"
[(const_int 0)
(const_int 1)])))]
"TARGET_SSE"
- "cvttps2pi\\t{%1, %0|%0, %1}"
+ "cvttps2pi\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "cvtsi2ss"
(float:SF (match_operand:SI 2 "register_operand" "rm")))
(const_int 15)))]
"TARGET_SSE"
- "cvtsi2ss\\t{%2, %0|%0, %2}"
+ "cvtsi2ss\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "cvtss2si"
(vec_select:SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
(parallel [(const_int 0)])))]
"TARGET_SSE"
- "cvtss2si\\t{%1, %0|%0, %1}"
+ "cvtss2si\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "cvttss2si"
(vec_select:SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
(parallel [(const_int 0)])))]
"TARGET_SSE"
- "cvttss2si\\t{%1, %0|%0, %1}"
+ "cvttss2si\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "paddb\\t{%2, %0|%0, %2}"
+ "paddb\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "addv4hi3"
(plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "paddw\\t{%2, %0|%0, %2}"
+ "paddw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "addv2si3"
(plus:V2SI (match_operand:V2SI 1 "register_operand" "0")
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "paddd\\t{%2, %0|%0, %2}"
+ "paddd\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "ssaddv8qi3"
(ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "paddsb\\t{%2, %0|%0, %2}"
+ "paddsb\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "ssaddv4hi3"
(ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "paddsw\\t{%2, %0|%0, %2}"
+ "paddsw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "usaddv8qi3"
(us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "paddusb\\t{%2, %0|%0, %2}"
+ "paddusb\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "usaddv4hi3"
(us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "paddusw\\t{%2, %0|%0, %2}"
+ "paddusw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "subv8qi3"
(minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "psubb\\t{%2, %0|%0, %2}"
+ "psubb\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "subv4hi3"
(minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "psubw\\t{%2, %0|%0, %2}"
+ "psubw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "subv2si3"
(minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "psubd\\t{%2, %0|%0, %2}"
+ "psubd\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "sssubv8qi3"
(ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "psubsb\\t{%2, %0|%0, %2}"
+ "psubsb\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "sssubv4hi3"
(ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "psubsw\\t{%2, %0|%0, %2}"
+ "psubsw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "ussubv8qi3"
(us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "psubusb\\t{%2, %0|%0, %2}"
+ "psubusb\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "ussubv4hi3"
(us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "psubusw\\t{%2, %0|%0, %2}"
+ "psubusw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "mulv4hi3"
(mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "pmullw\\t{%2, %0|%0, %2}"
+ "pmullw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "smulv4hi3_highpart"
(sign_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
(const_int 16))))]
"TARGET_MMX"
- "pmulhw\\t{%2, %0|%0, %2}"
+ "pmulhw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "umulv4hi3_highpart"
(zero_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
(const_int 16))))]
"TARGET_MMX"
- "pmulhuw\\t{%2, %0|%0, %2}"
+ "pmulhuw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "mmx_pmaddwd"
(parallel [(const_int 1)
(const_int 3)]))))))]
"TARGET_MMX"
- "pmaddwd\\t{%2, %0|%0, %2}"
+ "pmaddwd\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
[(ior:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
- "por\\t{%2, %0|%0, %2}"
+ "por\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "mmx_xordi3"
[(xor:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
- "pxor\\t{%2, %0|%0, %2}"
+ "pxor\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
;; Same as pxor, but don't show input operands so that we don't think
[(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI [(const_int 0)] 45))]
"TARGET_MMX"
- "pxor\\t{%0, %0|%0, %0}"
+ "pxor\t{%0, %0|%0, %0}"
[(set_attr "type" "mmx")])
(define_insn "mmx_anddi3"
[(and:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
- "pand\\t{%2, %0|%0, %2}"
+ "pand\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "mmx_nanddi3"
[(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
- "pandn\\t{%2, %0|%0, %2}"
+ "pandn\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(const_int 1)])))
(const_int 1)))]
"TARGET_SSE"
- "pavgb\\t{%2, %0|%0, %2}"
+ "pavgb\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "mmx_uavgv4hi3"
(const_int 1)])))
(const_int 1)))]
"TARGET_SSE"
- "pavgw\\t{%2, %0|%0, %2}"
+ "pavgw\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "mmx_psadbw"
(abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym"))))]
"TARGET_SSE"
- "psadbw\\t{%2, %0|%0, %2}"
+ "psadbw\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
(match_operand:SI 3 "immediate_operand" "i")))]
"TARGET_SSE"
- "pinsrw\\t{%3, %2, %0|%0, %2, %3}"
+ "pinsrw\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse")])
(define_insn "mmx_pextrw"
(parallel
[(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SSE"
- "pextrw\\t{%2, %1, %0|%0, %1, %2}"
+ "pextrw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sse")])
(define_insn "mmx_pshufw"
(match_operand:V4HI 2 "nonimmediate_operand" "ym")
(match_operand:SI 3 "immediate_operand" "i")] 41))]
"TARGET_SSE"
- "pshufw\\t{%3, %2, %0|%0, %2, %3}"
+ "pshufw\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse")])
(eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "pcmpeqb\\t{%2, %0|%0, %2}"
+ "pcmpeqb\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "eqv4hi3"
(eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "pcmpeqw\\t{%2, %0|%0, %2}"
+ "pcmpeqw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "eqv2si3"
(eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "pcmpeqd\\t{%2, %0|%0, %2}"
+ "pcmpeqd\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "gtv8qi3"
(gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "pcmpgtb\\t{%2, %0|%0, %2}"
+ "pcmpgtb\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "gtv4hi3"
(gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "pcmpgtw\\t{%2, %0|%0, %2}"
+ "pcmpgtw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "gtv2si3"
(gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
- "pcmpgtd\\t{%2, %0|%0, %2}"
+ "pcmpgtd\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE"
- "pmaxub\\t{%2, %0|%0, %2}"
+ "pmaxub\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "smaxv4hi3"
(smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE"
- "pmaxsw\\t{%2, %0|%0, %2}"
+ "pmaxsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "uminv8qi3"
(umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE"
- "pminub\\t{%2, %0|%0, %2}"
+ "pminub\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(define_insn "sminv4hi3"
(smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE"
- "pminsw\\t{%2, %0|%0, %2}"
+ "pminsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
(ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
- "psraw\\t{%2, %0|%0, %2}"
+ "psraw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "ashrv2si3"
(ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
- "psrad\\t{%2, %0|%0, %2}"
+ "psrad\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "lshrv4hi3"
(lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
- "psrlw\\t{%2, %0|%0, %2}"
+ "psrlw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "lshrv2si3"
(lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
- "psrld\\t{%2, %0|%0, %2}"
+ "psrld\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
;; See logical MMX insns.
[(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
"TARGET_MMX"
- "psrlq\\t{%2, %0|%0, %2}"
+ "psrlq\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "ashlv4hi3"
(ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
- "psllw\\t{%2, %0|%0, %2}"
+ "psllw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "ashlv2si3"
(ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
- "pslld\\t{%2, %0|%0, %2}"
+ "pslld\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
;; See logical MMX insns.
[(ashift:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
"TARGET_MMX"
- "psllq\\t{%2, %0|%0, %2}"
+ "psllq\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
(ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
"TARGET_MMX"
- "packsswb\\t{%2, %0|%0, %2}"
+ "packsswb\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "mmx_packssdw"
(ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
(ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
"TARGET_MMX"
- "packssdw\\t{%2, %0|%0, %2}"
+ "packssdw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "mmx_packuswb"
(us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
(us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
"TARGET_MMX"
- "packuswb\\t{%2, %0|%0, %2}"
+ "packuswb\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "mmx_punpckhbw"
(const_int 7)]))
(const_int 85)))]
"TARGET_MMX"
- "punpckhbw\\t{%2, %0|%0, %2}"
+ "punpckhbw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "mmx_punpckhwd"
(const_int 1)]))
(const_int 5)))]
"TARGET_MMX"
- "punpckhwd\\t{%2, %0|%0, %2}"
+ "punpckhwd\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "mmx_punpckhdq"
(const_int 0)]))
(const_int 1)))]
"TARGET_MMX"
- "punpckhdq\\t{%2, %0|%0, %2}"
+ "punpckhdq\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "mmx_punpcklbw"
(const_int 3)]))
(const_int 85)))]
"TARGET_MMX"
- "punpcklbw\\t{%2, %0|%0, %2}"
+ "punpcklbw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "mmx_punpcklwd"
(const_int 3)]))
(const_int 5)))]
"TARGET_MMX"
- "punpcklwd\\t{%2, %0|%0, %2}"
+ "punpcklwd\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "mmx_punpckldq"
(const_int 1)]))
(const_int 1)))]
"TARGET_MMX"
- "punpckldq\\t{%2, %0|%0, %2}"
+ "punpckldq\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
(define_insn "ldmxcsr"
[(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 37)]
"TARGET_MMX"
- "ldmxcsr\\t%0"
+ "ldmxcsr\t%0"
[(set_attr "type" "mmx")])
(define_insn "stmxcsr"
[(set (match_operand:SI 0 "memory_operand" "=m")
(unspec_volatile:SI [(const_int 0)] 40))]
"TARGET_MMX"
- "stmxcsr\\t%0"
+ "stmxcsr\t%0"
[(set_attr "type" "mmx")])
(define_expand "sfence"
[(set (match_dup 0)
(unspec:BLK [(match_dup 0)] 44))]
"TARGET_SSE"
- "
{
operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (operands[0]) = 1;
-}")
+})
(define_insn "*sfence_insn"
[(set (match_operand:BLK 0 "" "")
[(unspec [(match_operand:SI 0 "address_operand" "p")
(match_operand:SI 1 "immediate_operand" "n")] 35)]
"TARGET_SSE"
- "*
{
switch (INTVAL (operands[1]))
{
case 0:
- return \"prefetchnta\\t%a0\";
+ return "prefetchnta\t%a0";
case 1:
- return \"prefetcht0\\t%a0\";
+ return "prefetcht0\t%a0";
case 2:
- return \"prefetcht1\\t%a0\";
+ return "prefetcht1\t%a0";
case 3:
- return \"prefetcht2\\t%a0\";
+ return "prefetcht2\t%a0";
default:
abort ();
}
-}"
+}
[(set_attr "type" "sse")])
projects / gcc.git / commitdiff