sse.md (avx_vec_concat<mode>): Add v=v,vm and Yv=Yv,C alternatives.

	* config/i386/sse.md (avx_vec_concat<mode>): Add v=v,vm and
	Yv=Yv,C alternatives.

From-SVN: r237175

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 64ec93ff5a28f73c4ebaa474e3d9994a6ab91e7d..022f9aa0fcfde7bc80423b1bf9de6db093eb490f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2016-06-07  Jakub Jelinek  <jakub@redhat.com>
+
+       * config/i386/sse.md (avx_vec_concat<mode>): Add v=v,vm and
+       Yv=Yv,C alternatives.
+
 2016-06-07  Richard Biener  <rguenther@suse.de>
 
        PR c/61564

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 5e7460841a0ce875a7e2763b2561fd6f4e1bdff1..82ef04a2a034db58fa14f7cdb9ac79ba6c3e49ec 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -18414,10 +18414,10 @@
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn "avx_vec_concat<mode>"
-  [(set (match_operand:V_256_512 0 "register_operand" "=x,x")
+  [(set (match_operand:V_256_512 0 "register_operand" "=x,v,x,Yv")
        (vec_concat:V_256_512
-         (match_operand:<ssehalfvecmode> 1 "register_operand" "x,x")
-         (match_operand:<ssehalfvecmode> 2 "vector_move_operand" "xm,C")))]
+         (match_operand:<ssehalfvecmode> 1 "register_operand" "x,v,x,v")
+         (match_operand:<ssehalfvecmode> 2 "vector_move_operand" "xm,vm,C,C")))]
   "TARGET_AVX"
 {
   switch (which_alternative)
@@ -18425,6 +18425,22 @@
     case 0:
       return "vinsert<i128>\t{$0x1, %2, %<concat_tg_mode>1, %0|%0, %<concat_tg_mode>1, %2, 0x1}";
     case 1:
+      if (<MODE_SIZE> == 64)
+       {
+         if (TARGET_AVX512DQ && GET_MODE_SIZE (<ssescalarmode>mode) == 4)
+           return "vinsert<shuffletype>32x8\t{$0x1, %2, %<concat_tg_mode>1, %0|%0, %<concat_tg_mode>1, %2, 0x1}";
+         else
+           return "vinsert<shuffletype>64x4\t{$0x1, %2, %<concat_tg_mode>1, %0|%0, %<concat_tg_mode>1, %2, 0x1}";
+       }
+      else
+       {
+         if (TARGET_AVX512DQ && GET_MODE_SIZE (<ssescalarmode>mode) == 8)
+           return "vinsert<shuffletype>64x2\t{$0x1, %2, %<concat_tg_mode>1, %0|%0, %<concat_tg_mode>1, %2, 0x1}";
+         else
+           return "vinsert<shuffletype>32x4\t{$0x1, %2, %<concat_tg_mode>1, %0|%0, %<concat_tg_mode>1, %2, 0x1}";
+       }
+    case 2:
+    case 3:
       switch (get_attr_mode (insn))
        {
        case MODE_V16SF:
@@ -18436,9 +18452,19 @@
        case MODE_V4DF:
          return "vmovapd\t{%1, %x0|%x0, %1}";
        case MODE_XI:
-         return "vmovdqa\t{%1, %t0|%t0, %1}";
+         if (which_alternative == 2)
+           return "vmovdqa\t{%1, %t0|%t0, %1}";
+         else if (GET_MODE_SIZE (<ssescalarmode>mode) == 8)
+           return "vmovdqa64\t{%1, %t0|%t0, %1}";
+         else
+           return "vmovdqa32\t{%1, %t0|%t0, %1}";
        case MODE_OI:
-         return "vmovdqa\t{%1, %x0|%x0, %1}";
+         if (which_alternative == 2)
+           return "vmovdqa\t{%1, %x0|%x0, %1}";
+         else if (GET_MODE_SIZE (<ssescalarmode>mode) == 8)
+           return "vmovdqa64\t{%1, %x0|%x0, %1}";
+         else
+           return "vmovdqa32\t{%1, %x0|%x0, %1}";
        default:
          gcc_unreachable ();
        }
@@ -18446,9 +18472,9 @@
       gcc_unreachable ();
     }
 }
-  [(set_attr "type" "sselog,ssemov")
-   (set_attr "prefix_extra" "1,*")
-   (set_attr "length_immediate" "1,*")
+  [(set_attr "type" "sselog,sselog,ssemov,ssemov")
+   (set_attr "prefix_extra" "1,1,*,*")
+   (set_attr "length_immediate" "1,1,*,*")
    (set_attr "prefix" "maybe_evex")
    (set_attr "mode" "<sseinsnmode>")])