(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
(match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
"! TARGET_POWERPC64"
- "@
- {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2
- {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1
- {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2
- {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1"
+ "*
+{
+ if (WORDS_BIG_ENDIAN)
+ return (GET_CODE (operands[2])) != CONST_INT
+ ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
+ : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
+ else
+ return (GET_CODE (operands[2])) != CONST_INT
+ ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
+ : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
+}"
[(set_attr "length" "8")])
(define_insn "subddi3"
(minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
(match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
"TARGET_POWER && ! TARGET_POWERPC64"
- "@
- {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1
- {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2
- {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1
- {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1
- {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2"
- [(set_attr "length" "8")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r")
- (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,0,r")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,0")))]
- "! TARGET_POWER && ! TARGET_POWERPC64"
"*
{
- return (WORDS_BIG_ENDIAN)
- ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
- : \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\";
+ if (WORDS_BIG_ENDIAN)
+ return (GET_CODE (operands[1]) != CONST_INT)
+ ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
+ : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
+ else
+ return (GET_CODE (operands[1]) != CONST_INT)
+ ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
+ : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
}"
[(set_attr "length" "8")])