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Added english description for lhzu instruction
authorShriya Sharma <shriya@redsemiconductor.com>
Tue, 19 Sep 2023 15:44:56 +0000 (16:44 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 22 Dec 2023 19:26:21 +0000 (19:26 +0000)
openpower/isa/fixedload.mdwn patch | blob | history

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 0e2b6536ad9ed8b2af16c4226da9aca1eaa34695..93297dccdb819a58e7fd6cee4780f619375616f9 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -152,9 +152,11 @@ Pseudo-code:
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- EA
 
-Description:Let the effective address (EA) be the sum
-(RA|0)+ (RB). The halfword in storage addressed by
-EA is loaded into RT 48:63. RT 0:47 are set to 0.
+Description:Let the effective address (EA) be the sum (RA)+ D. The
+halfword in storage addressed by EA is loaded into
+RT48:63. RT 0:47 are set to 0.
+EA is placed into register RA.
+If RA=0 or RA=RT, the instruction form is invalid.
 
 Special Registers Altered: