update code-comments

diff --git a/lambdasoc/periph/hyperram.py b/lambdasoc/periph/hyperram.py
index 299a165f85bb7ec17347a4aaacdc26c8258822b3..c9b5d944d4358b1b07a2df9666c8006df0b98caf 100644 (file)
--- a/lambdasoc/periph/hyperram.py
+++ b/lambdasoc/periph/hyperram.py
@@ -24,9 +24,9 @@ use platform.add_extension to first define the pins:
     io = self.platform.request("hyperram")
 
 this trick will work with the 1-IC HyperRAM PMOD by Piotr Esden, sold
-by 1bitsquared.  however for the *four* IC HyperRAM PMOD, *four*
-separate and distinct instances are needed, each with a different
-cs_n pin.  on the TODO list for this module: interleave multiple HyperRAM
+by 1bitsquared.  however for the *four* IC HyperRAM PMOD, *four* cs_n pins
+are needed (and is not currently supported).
+on the TODO list for this module: interleave multiple HyperRAM
 cs_n's to give striped (like RAID) memory accesses behind one single
 Wishbone interface.
 """
@@ -142,6 +142,7 @@ class HyperRAM(Peripheral, Elaboratable):
     - no setup/chip configuration (use default latency).
 
     This core favors portability and ease of use over performance.
+    Tested: Winbond W956D8MBYA latency=7
     """
     def __init__(self, *, io, phy_kls, latency=6, bus=None,
                                        features=frozenset()):